Writable analog reference voltage storage device

Claim 2

A circuit disposed on a semiconductor substrate for generating an analog voltage signal in a semiconductor integrated circuit disposed on said semiconductor substrate, including: an analog floating gate storage device disposed on said semiconductor substrate, said analog floating gate storage device including a floating gate connected to a stabilizing capacitor, and a non-avalanche hot electron injection device including a collector connected to a first voltage node, an emitter connected to a second voltage node and a base connected to a third voltage node; an electron tunneling device coupled to said floating gate for removing electrons from said floating gate, an analog output voltage bus; and a high input impedance follower amplifier having an input connected to said floating gate and an output connected to said analog output voltage bus.

Claim 3

The circuit of claim 1 wherein said analog output voltage bus has a capacitance associated therewith, said capacitance having a value greater than the inherent capacitance associated with said bus and further including means for turning off the output of said follower amplifier.

Claim 4

The circuit of claim 2, further including: a monitor/dynamic load line; an analog pass gate connected between said analog output voltage bus and said monitor/dynamic load line; and means for providing a strobe signal to said analog pass gate.

Claim 5

The circuit of claim 1, further including: a diode-connected P-channel MOS transistor having a source connected to a first voltage rail, said diode-connected P-channel MOS transistor having a capacitor connected between its gate and source; an N-channel MOS transistor having its gate connected to said analog output voltage bus and its source connected to the drain of said diode connected P-channel MOS transistor.

Claim 6

The circuit of claim 1, further including: a diode-connected N-channel MOS transistor having a source connected to a second voltage rail, said diode-connected N-channel MOS transistor having a capacitor connected between its gate and source; an MOS transistor having its gate connected to said analog output voltage bus and its source connected to the drain of said diode-connected N-channel MOS transistor.

Claim 7

The circuit of claim 3, further including a diode- connected N-channel MOS transistor having a source connected to a second voltage rail, and a drain connected to the source of said MOS transistor, said diode connected N-channel MOS transistor having a capacitor connected between its gate and source.

Claim 8

The circuit of claim 5, wherein said MOS transistor is an N-channel MOS transistor.

Claim 9

The circuit of claim 6, wherein said MOS transistor is an N-channel MOS transistor.

Claim 10

A circuit disposed on a semiconductor substrate for generating N analog voltage signals in a semiconductor integrated circuit disposed on said semiconductor substrate, including: N analog floating gate storage devices disposed on said semiconductor substrate, each of said analog floating gate storage devices including: a select node, a first P-channel MOS transistor, having a source connected to a first voltage source, a drain, and a gate connected to said select node, a second P-channel MOS transistor, having a source connected to said a second voltage source, a drain, and a gate connected to said select node, a floating gate connected to a stabilizing capacitor, a non-avalanche hot electron injection device including a collector connected to the drain of said first P-channel MOS transistor, a base connected to the drain of aid second P-channel MOS transistor, an emitter connected to a third voltage node, and an insulated gate disposed above said base, said insulated gate self aligned with said collector and not overlapping said emitter, said insulated gate connected to said floating gate, an electron tunneling device coupled to said floating gate for removing electrons from said floating gate, and wherein said first, second, and third voltage sources are selected so as to cause non-avalanche hot electron injection onto said floating gate; addressing means for activating selected ones of said select nodes so as to turn on their first and second P-channel MOS transistors: an analog output voltage bus; and a high input impedance follower amplifier having an input connected to said floating gate and an output connected to said analog output voltage bus.

Claim 11

A circuit disposed on a semiconductor substrate for generating N analog voltage signals in a semiconductor integrated circuit disposed on said semiconductor substrate, including: N analog floating gate storage devices disposed on said semiconductor substrate, each of said analog floating gate storage devices including: a select node, a first P-channel MOS transistor, having a source connected to a first voltage source, a drain, and a gate connected to said select node, a second P-channel MOS transistor, having a source connected to said a second voltage source, a drain, and a gate connected to said select node, a floating gate connected to a stabilizing capacitor, a non-avalanche hot electron injection device including a collector connected to the drain of said first P-channel MOS transistor, a base connected to the drain of aid second P-channel MOS transistor, an emitter connected to a third voltage node, and an insulated gate disposed above said base, said insulated gate self aligned with said collector and not overlapping said emitter, said insulated gate connected to said floating gate, an electron tunneling device coupled to said floating gate for removing electrons from said floating gate, and wherein said first, second, and third voltage sources are selected so as to cause non-avalanche hot electron injection onto said floating gate; addressing means for activating selected ones of said select nodes so as to turn on their first and second P-channel MOS transistors: an analog output voltage bus; and a high input impedance follower amplifier having an input connected to said floating gate and an output connected to said analog output voltage bus.

Claim 12

The circuit of claim 9 wherein said analog output voltage bus has a capacitance associated therewith, said capacitance having a value greater than the inherent capacitance associated with said bus and further including means for turning off the output of said follower amplifier.

Claim 13

The circuit of claim 9, further including: a monitor/dynamic load line; an analog pass gate connected between said analog output voltage bus and said monitor/dynamic load line; and means for providing a strobe signal to said analog pass gate.

Claim 14

The circuit of claim 9, further including: a diode-connected P-channel MOS transistor having a source connected to a first voltage rail, said diode-connected P-channel MOS transistor having a capacitor connected between its gate and source; an N-channel MOS transistor having its gate connected to said analog output voltage bus and its source connected to the drain of said diode connected P-channel MOS transistor.

Claim 15

The circuit of claim 9, further including: a diode-connected N-channel MOS transistor having a source connected to a second voltage rail, said diode-connected N-channel MOS transistor having a capacitor connected between its gate and source; an MOS transistor having its gate connected to said analog output voltage bus and its source connected to the drain of said diode-connected N-channel MOS transistor.

Claim 16

The circuit of claim 11, further including a diode-connected N-channel MOS transistor having a source connected to a second voltage rail, and a drain connected to the source of said MOS transistor, said diode connected N-channel MOS transistor having a capacitor connected between its gate and source.

Claim 17

The circuit of claim 13, wherein said MOS transistor is an N-channel MOS transistor.

Claim 18

The circuit of claim 14, wherein said MOS transistor is an N-channel MOS transistor.