EP0306990A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device with dummy cell array
Assignee: Toshiba Corp
•
Filing: 1988-09-09
•
Granted: —
•
Expires: 2008-09-09
Abstract
Abstract A semiconductor memory device in which data can be read out in response to an address signal comprises power source lines, a plurality of row (WL1 - WLmn) and column conductive lines (COL1 - COLn), a memory cell array (10) including nonvolatile memory cells (M11 - Mmn) arranged in a matrix form of rows and columns and respectively connected to the plurality of row and column lines (COL1 - COLn, WL1 - WLn) and the power source lines, a first selector circuit (5) for generating a signal for selecting the row conductive lines in response to an address signal, a dummy row line (DWL), and dummy memory cells (DM1 - DMn) each having a source, a drain and a control gate connected to the dummy row line (DWL). In the semiconductor memory device, one of paths between the source and the power source line and between the drain and the corresponding row line is closed and the other path is opened, and it further includes a second selector circuit (11) for selectively generating a line selection signal for selecting one of the row conductive lines in response to an address signal and a dummy selection signal for selecting the dummy row line (DWL) in response to the same address signal.
Inventors
- 👤 Hidenobu Minagawa
- 👤 Yuuichi Tatsumi
- 👤 Hiroshi Iwahashi
- 👤 Masamichi Asano
- 👤 Mizuho Imai
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 22:17
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C29/00; G11C29/04; G11C29/50; G11C29/50012; G11C16/00; G11C16/02; G11C16/06; G11C16/08; G11C16/26; G11C16/28; G11C16/32; G11C16/34; G11C29/08; G11C29/12; G11C29/18; G11C29/24; G11C29/52; G11C16/04
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
176 words
A semiconductor memory device comprising: a memory cell array (7) including nonvolatile memory cells (M11 - Mmn); a plurality of row lines (WL1 - WLm) each connected to said memory cells (M11 - Mmn) arranged on a corresponding row; a plurality of column lines (COL1 - COLn) each connected to said memory cells (M11 - Mmn) arranged on a corresponding column; address buffer means (2, 3) for receiving external address signals at its address input terminals and for outputting internal address signals; and row and column select means (4, 5) for selecting one of the row lines (WL1 - WLm-1) except at least predetermined one (WLm) and the column line (COL1 - COLn) to select the memory cell (M11 - Mmn) in response to the internal address signals; characterized by further comprising: first signal generating means (12, 14) for generating a test mode signal in response to an input control signal; second select means (11) for controlling the selection of the predetermined row line in accordance with the internal address signals and the test mode signal.
Claim 2
Dependent Claim
176 words
A semiconductor memory device comprising: a memory cell array (7) including nonvolatile memory cells (M11 - Mmn); a plurality of row lines (WL1 - WLm) each connected to said memory cells (M11 - Mmn) arranged on a corresponding row; a plurality of column lines (COL1 - COLn) each connected to said memory cells (M11 - Mmn) arranged on a corresponding column; address buffer means (2, 3) for receiving external address signals at its address input terminals and for outputting internal address signals; and row and column select means (4, 5) for selecting one of the row lines (WL1 - WLm-1) except at least predetermined one (WLm) and the column line (COL1 - COLn) to select the memory cell (M11 - Mmn) in response to the internal address signals; characterized by further comprising: first signal generating means (12, 14) for generating a test mode signal in response to an input control signal; second select means (11) for controlling the selection of the predetermined row line in accordance with the internal address signals and the test mode signal.
Claim 3
Dependent Claim
36 words
A semiconductor memory device according to claim 1, characterized by further comprising: a dummy row line (DWL); and dummy memory cell array (10) including dummy cells (DM1 - DMn) each connected to the dummy row line.
Claim 4
Dependent Claim
35 words
A semiconductor memory device according to claim 1, characterized in that each of said dummy cells (DM1 - DMn) have a source, a drain and a control gate connected to said dummy row line (DWL).
Claim 5
Dependent Claim
48 words
A semiconductor memory device according to claim 3, characterized by further comprising power source lines, wherein one of the drain and source is connected to the corresponding column line (COL1 - COLn) and the other of the source and drain is disconnected to the corresponding power source line.
Claim 6
Dependent Claim
48 words
A semiconductor memory device according to claim 3, characterized by further comprising power source lines, wherein one of the drain and source is connected to the corresponding power source line and the other of the source and drain is disconnected to the corresponding column line (COL1 - COLn).
Claim 7
Dependent Claim
62 words
A semiconductor memory device according to claim 1, characterized by further comprising output buffer means (6) for outputting a data stored in the memory cell (DM1 - DMn) and second signal generating means (13, 15) for generating an activating signal for activating said output buffer means (6) in response to one of the test mode signal and a second input control signal.
Claim 8
Dependent Claim
62 words
A semiconductor memory device according to claim 2, characterized by further comprising output buffer means (6) for outputting a data stored in the memory cell (DM1 - DMn) and second signal generating means (13, 15) for generating an activating signal for activating said output buffer means (6) in response to one of the test mode signal and a second input control signal.
Claim 9
Dependent Claim
44 words
A semiconductor memory device according to claim 6, characterized in that said buffer means (2, 3) includes row address buffer means (3) for receiving the address signals and outputting the address signals to said row selector means (5) and said second selector means (11).
Claim 10
Dependent Claim
52 words
A semiconductor memory device according to claim 8, characterized in that said second signal generating means (13, 15) includes a switching signal generating circuit (13a, 15a) which generates a switching signal in response to the second input control signal when said second signal generating means (13, 15) receives the test mode signal.
Claim 11
Dependent Claim
76 words
A semiconductor memory device according to claim 9, characterized in that said first signal generating means (12) includes buffer control means (12b) for controlling said row address buffer means (3), which generates a buffer control signal in response to the second input signal and the switching signal, and said row address buffer means (3) generates the predetermined address signals and outputs one of the input and predetermined address signals in accordance with the buffer control signal.
Claim 12
Dependent Claim
73 words
A semiconductor memory device according to claim 10, characterized in that the buffer control signal has the inversion form of the second input control signal and said row address buffer means (3) generates and outputs the predetermined address signals when the buffer control signal has one of normal logic levels and said address buffer means outputs the inputted address signals when the buffer control signal has the other of the normal logic levels.
Claim 13
Dependent Claim
85 words
A semiconductor memory device according to claim l, characterized in that said first signal generating means (12, 14) includes a high voltage detection circuit (12c, 14c) which generates the test mode signal having normal logic levels when the input control signal has a predetermined high level higher than the normal logic levels and said first generating means (12, 14) generates a normal mode signal having different logic levels with that of the test mode signal when the input control signal has the normal logic levels.
Claim 14
Dependent Claim
73 words
A semiconductor memory device according to claim 12, characterized in that said first generating means (12, 14) includes signal converting means (12b, 14b) for converting the input control signal having the predetermined high level into a chip control signal having the high normal logic level and the input normal signal having the normal logic levels into the chip control signal having the logic levels and being in phase with the input control signal.
Claim 15
Dependent Claim
59 words
A semiconductor memory device according to claim 13, characterized in that said first signal generating means (12, 14) includes a NAND gate circuit (120) to which the first input control signal and the test mode signal is inputted and an inverter (139) for inverting an output signal from the NAND gate circuit (120) and generating a chip enable signal.
Claim 16
Dependent Claim
62 words
A semiconductor memory device according to claim 13, characterized by further comprising output buffer means (6) for outputting a data stored in the memory cell (M11 - Mmn) and second signal generating means (13, 15) for generating an activating signal for activating said output buffer means (6) in response to one of the chip control signal and a second input control signal.
Claim 17
Dependent Claim
135 words
A semiconductor memory device according to claim 15, characterized in that said first signal generating means (12, 14) generates a chip enable signal in response to the first control signal and said second signal generating means (13, 15) includes a NOR gate circuit (147) to which the chip enable signal and the second input control signal are inputted, a first inverter (155) for inverting an output signal from a NOR gate circuit, a NAND gate circuit (130) to which an output signal from the inverter (155) and the first input control signal, a second inverter (61) for inverting an output signal from the NAND gate circuit (130) and a third inverter (164) for inverting an output signal from the second inverter (61), the activating signal being generated from the second and third inverter (61, 64).
Claim 18
Dependent Claim
54 words
A semiconductor memory device according to claim 9, characterized in that said first signal generating means (12, 14) includes a chip enable signal generating means (12c) for generating a chip enable signal in response to the first input signal which is in phase with the first input signal and has the normal logic levels.
Claim 19
Dependent Claim
26 words
A semiconductor memory device according to claim 16, characterized in that said second signal generating means (13, 15) is activated by the chip enable signal (12c).
Claim 20
Dependent Claim
36 words
A semiconductor memory device according to claim 16, characterized by further comprising column address buffer means (2) for outputting the address signals to the column selector means (2), which is activated by the chip enable signal.
Claim 21
Dependent Claim
60 words
A semiconductor memory device according to claim 9, characterized in that said first signal generating means (12, 14) includes a chip enable signal generating means (12c) for generating a chip enable signal in response to the first input signal having the normal logic levels, the logic level of the chip enable signal is switched in accordance with the switching signal.
Claim 22
Dependent Claim
85 words
A semiconductor memory device according to claim 20, characterized in that said first generating circuit (12, 14) includes a NOR gate circuit (12b) and said switching signal generating circuit includes first inverter (168) for inverting an output signal from the NOR gate circuit (130), second inverter (171) for inverting an output signal from the first inverter (168) and NAND gate circuit (172) to which the first input control signal and an output signal from the second inverter (171) are inputted and generates the switching signal.
Claim 23
Dependent Claim
39 words
A semiconductor memory device according to claim 16, characterized in that said row address buffer means (3) generates the predetermined address signals and outputs one of the input and predetermined address signals in accordance with the chip enable signal.
Claim 24
Dependent Claim
39 words
A semiconductor memory device according to claim 12, characterized in that said first signal generating means (12, 14) includes latch means (21) for latching the test mode signal when the first input control signal has the predetermined high level.
Claim 25
Dependent Claim
31 words
A semiconductor memory device according to claim 22, characterized in that said latch means (21) is deenergized when the another first input control signal having the predetermined high level is inputted.
Claim 26
Dependent Claim
20 words
A semiconductor memory device according to claim 2, characterized in that said dummy cells (DMm1 -DMmn) are nonvolatile memory cells.
Claim 27
Dependent Claim
23 words
A semiconductor memory device according to claim 25, characterized by further comprising programming means for programming said dummy memory cells (DMm1 - DMmn).
Claim 28
Dependent Claim
26 words
A semiconductor memory device according to claim 2, characterized by further comprising another dummy row lines (DWLm-k - DWLm) to which said dummy cells are connected.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.