Screenable power chip mosaics, a method for fabricating large power semiconductor chips

Claim 1

An additive process for discretionary interconnection of acceptable devices on a semiconductor wafer which contains a plurality of acceptable and unacceptable devices, comprising the steps of: screen printing a polymeric layer on said semiconductor wafer such that vias are formed over each of said plurality of devices, said vias exposing contact pads for each of said plurality of devices; testing each of said plurality of devices to distinguish acceptable devices from unacceptable devices according to predetermined parameters; generating a positional map identifying the unacceptable device positions on said surface of said semiconductor wafer; selectively blocking off said unacceptable devices in accordance with said map by filling only the vias exposing the contact pads of said unacceptable devices; coating said semiconductor wafer with a layer of metal so as to electrically interconnect the acceptable devices on said semiconductor wafer; and patterning said metal layer to form a power chip array wherein at least some of said acceptable devices are interconnected by metal conductive runs.

Claim 13

A method for fabricating a power chip mosaic from a plurality of substantially identical semiconductor arrays, each of said arrays comprising a plurality of acceptable and unacceptable devices formed on a common semiconductor wafer, comprising the steps of: discretionarily interconnecting said acceptable devices in each array by screen printing a polymeric layer on said surface of said semiconductor wafer so as to form vias over each of said plurality of devices, said vias exposing contact pads for each of said plurality of devices, testing each device of said plurality of devices to identify unacceptable devices according to predetermined parameters, generating a positional map to locate said unacceptable devices on said semiconductor wafer, selectively blocking off said unacceptable devices located by said map by filling the vias exposing the contact pads of said unacceptable devices, coating said semiconductor wafer with a layer of metal to electrically interconnect the acceptable devices on said semiconductor wafer, patterning said metal layer to form a power chip array wherein a plurality of source contact pads of said acceptable devices are interconnected by a first conductive run and a plurality of gate contact pads of said acceptable devices are interconnected by a second conductive run, said first and second conductive runs being electrically isolated from each other; dividing said wafer into said plurality of arrays; coupling together in electrical parallel said first conductive run and said second conductive run of at least selected ones of said plurality of arrays utilizing strips of conductive foil; supporting said selected ones of said plurality of arrays on a support substrate comprising a mosaic of ceramic blocks connected by said strips of conductive foil; and applying a drain contact to said selected ones of said plurality of arrays to interconnect a drain portion of each of said devices in said array.

Claim 14

A method for fabricating a power chip mosaic from a plurality of substantially identical semiconductor arrays, each of said arrays comprising a plurality of acceptable and unacceptable devices formed on a common semiconductor wafer, comprising the steps of: discretionarily interconnecting said acceptable devices in each array by screen printing a polymeric layer on said surface of said semiconductor wafer so as to form vias over each of said plurality of devices, said vias exposing contact pads for each of said plurality of devices, testing each device of said plurality of devices to identify unacceptable devices according to predetermined parameters, generating a positional map to locate said unacceptable devices on said semiconductor wafer, selectively blocking off said unacceptable devices located by said map by filling the vias exposing the contact pads of said unacceptable devices, coating said semiconductor wafer with a layer of metal to electrically interconnect the acceptable devices on said semiconductor wafer, patterning said metal layer to form a power chip array wherein a plurality of source contact pads of said acceptable devices are interconnected by a first conductive run and a plurality of gate contact pads of said acceptable devices are interconnected by a second conductive run, said first and second conductive runs being electrically isolated from each other; dividing said wafer into said plurality of arrays; coupling together in electrical parallel said first conductive run and said second conductive run of at least selected ones of said plurality of arrays utilizing strips of conductive foil; supporting said selected ones of said plurality of arrays on a support substrate comprising a mosaic of ceramic blocks connected by said strips of conductive foil; and applying a drain contact to said selected ones of said plurality of arrays to interconnect a drain portion of each of said devices in said array.