Multi-level large scale complex integrated circuit having functional interconnected circuit routed to master patterns

Claim 2

An integrated circuit interconnection method for interconnecting operable cells into an electrical function on an integrated circuit wafer having a plurality of operable and inoperable cells, the operable and inoperable cells having random positions in a non-uniform distribution and having primary signal-connect means associated therewith at a first level of wafer metallization, comprising the steps of: preparing a master pattern both having predetermined circuit locations of operable cells including cells to be selected from any of the operable cells irrespective of their position and distribution and having partial interconnections among at least some of the operable cells or portions thereof, the predetermined circuit locations and the partial interconnections corresponding to a standardized configuration of integrated circuits for all wafers to be similarly processed into the electrical function; testing the plurality of operable and inoperable cells at the primary signal-connect means to determine positions of operable and inoperable cells; selecting operable cells from any of the tested operable cells irrespective of their position and distribution on the wafer, the number of the selected operable cells being at least equal to the number of predetermined circuit locations on the master pattern; electrically coupling and routing the primary signal-connect means of each of the selected operable cells to the sites of secondary signal-connect means of each of the selected operable cells by insulation and metallizing formation and masking processes to form electrical conduction means and simultaneously configuring the electrical conduction means into the standardized configuration, thereby terminating each of the selected operable cells in the secondary signal-connect means and in the positions corresponding to the predetermined circuit locations of the master pattern; and further electrically coupling the wafer cells from the secondary signal-connect means into the electrical function by use of standard masking means identical to all of the wafers to be similarly processed into the electrical function.

Claim 3

The method of claim 1 wherein said coupling and routing step further comprises the steps of: electrically isolating each of the inoperable cells, including each of the inoperable cells coinciding with any ones of the predetermined circuit locations, and electrically isolating each of the unselected operable cells by deposition of insulation material over the first level of metallization; exposing the primary signal-connect means of the selected operable cells by masking and insulation material removal means; and routing the electrical conduction means into the configuration of the integrated circuit from the exposed primary signal-connect means to the sites of the secondary signal-connect means, whereby some of the secondary signal-connect means at the predetermined circuit locations are situated Over a corresponding number of the inoperable cells in electrical isolation therefrom.

Claim 4

The method of claim 1 in which said coupling and routing step includes the step of routing the electrical conductors in multiply-connected line segments from the primary signal-connect means of the selected operable cells to the sites of the secondary signal-connect means.

Claim 5

The method of claim 1 in which said coupling and routing step includes the step of routing the electrical conductors in a plurality of interconnected line segments including curved line segments from the primary signal-connect means of the selected operable cells to the sites of the secondary signal-connect means and forming the line segments into the configuration of the integrated circuit.

Claim 6

The method of claim 1 for use with a plurality of the wafers, further including the steps of electrically coupling the primary signal-connect means of any ones of the selected operable cells of each of the wafers to the sites of the secondary signal-connect means and into the configuration of the integrated circuits and electrically coupling in an identical manner for each of the wafers the secondary signal-connect means thereof by use of the identical masking means into identical circuit configurations corresponding to the electrical function.

Claim 7

The method of claim 1 wherein said coupling and routing step comprises the steps of: forming a first layer of photoresist material over the operable and inoperable cells and the wafer; exposing portions of the first photoresist layer overlaying the primary signal-connect means of the selected operable cells through masking means to light to form exposed portions and unexposed portions of the first photoresist layer; removing the unexposed portions of the first photoresist layer; forming a layer of electrically insulating material over the cells and the exposed photoresist portions of the first layer; heating the device to crack the insulating material over the first layer exposed photoresist portions; removing the first layer exposed photoresist portions and the cracked insulating material to expose the primary signal-connect means of the selected cells; forming a layer of electrically conductive material on the insulating material and the exposed primary signal-connect means; forming a second layer of photoresist material on the layer of electrically conductive material; exposing portions of the second photoresist layer in a pattern of interconnect lines both conforming to the configuration of the integrated circuits and extending from the exposed primary signal-connect means of the selected cells to the sites of the secondary signal-connect means to form exposed and unexposed portions of the second photoresist layer; removing the second layer unexposed photoresist portions to expose portions of the conductive material; removing the exposed portions of the conductive material; and removing the exposed photoresist portions, leaving the conductive material in the pattern of interconnect lines, extending from the primary signal-connect means of the selected operable cells to the sites of the secondary signal-connect means and conforming to the integrated circuit configuration.

Claim 8

An integrated circuit interconnection method for interconnecting operable cells into an electrical function on each of a plurality of integrated circuit wafers, each capable of performing the same electrical function, each of the wafers having a plurality of operable and inoperable cells in random positions of a non-uniform distribution, each of the operable and inoperable cells having primary signal-connect means associated therewith in a first level of metallization, comprising the steps of: preparing a master pattern having predetermined circuit locations, for each and every one of the wafers, the master pattern defining identical positions of operable cells to be selected from any of the operable cells irrespective of the posItion and distribution thereof on individual ones of the wafers at a level subsequent to the first level of metallization; testing the plurality of operative and inoperative cells of each of the wafers at the primary signal-connect means to determine locations of operable and inoperable cells; for each of the wafers, selecting operable cells from any of the operable cells irrespective of the position and distribution thereof on individual ones of the wafers, the number of selected operable cells at least capable of performing the electrical function, and the number of the selected operable cells being at least equal to the number of predetermined circuit locations of the master pattern; for each of the wafers, electrically insulating the operable and inoperable cells and the primary signal-connect means from one another to form a first insulation layer over the cells and over the primary signal-connect means, with feedthrough means in the first insulation layer opening to the primary signal-connect means of the selected operable cells; for each of the wafers, electrically coupling and routing the primary signal-connect means of each of the selected operable cells through the feedthrough means and to sites of secondary signal-connect means of each of the selected operable cells and thereby terminating each of the selected operable cells in the identical positions corresponding to the predetermined circuit locations of the master pattern and simultaneously configuring conduction means among the secondary signal-connect means in the form of the integrated circuit; and further identical processing of each of the plurality of wafers from the secondary signal-connect means of each of the wafers by use of standard masking means identical to all of the wafers for interconnecting the selected operable cells thereof in such a manner as to enable each of the wafers to perform the electrical function.

Claim 9

An integrated circuit interconnection method for interconnecting operable cells into an electrical function on each of a plurality of integrated circuit wafers, each capable of performing the same electrical function, each of the wafers having a plurality of operable and inoperable cells in random positions of a non-uniform distribution, each of the operable and inoperable cells having primary signal-connect means associated therewith in a first level of metallization, comprising the steps of: preparing a master pattern having predetermined circuit locations, for each and every one of the wafers, the master pattern defining identical positions of operable cells to be selected from any of the operable cells irrespective of the posItion and distribution thereof on individual ones of the wafers at a level subsequent to the first level of metallization; testing the plurality of operative and inoperative cells of each of the wafers at the primary signal-connect means to determine locations of operable and inoperable cells; for each of the wafers, selecting operable cells from any of the operable cells irrespective of the position and distribution thereof on individual ones of the wafers, the number of selected operable cells at least capable of performing the electrical function, and the number of the selected operable cells being at least equal to the number of predetermined circuit locations of the master pattern; for each of the wafers, electrically insulating the operable and inoperable cells and the primary signal-connect means from one another to form a first insulation layer over the cells and over the primary signal-connect means, with feedthrough means in the first insulation layer opening to the primary signal-connect means of the selected operable cells; for each of the wafers, electrically coupling and routing the primary signal-connect means of each of the selected operable cells through the feedthrough means and to sites of secondary signal-connect means of each of the selected operable cells and thereby terminating each of the selected operable cells in the identical positions corresponding to the predetermined circuit locations of the master pattern and simultaneously configuring conduction means among the secondary signal-connect means in the form of the integrated circuit; and further identical processing of each of the plurality of wafers from the secondary signal-connect means of each of the wafers by use of standard masking means identical to all of the wafers for interconnecting the selected operable cells thereof in such a manner as to enable each of the wafers to perform the electrical function.

Claim 10

A method as in claim 21 wherein said step of preparing the master pattern of the predetermined circuit locations and the integrated circuit configuration comprises the step of placing the locations in accordance with the expected density of the selected operable cells.