US3795974A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Repairable multi-level large scale integrated circuit
Assignee: Raytheon Co
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Filing: 1971-12-16
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Granted: 1974-03-12
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Expires: 1991-12-16
Abstract
Abstract A multi-level complex standard circuit comprising a wafer having a plurality of cells in a rectilinear array and alternate layers of dielectric insulation and metalization formed in a laminae on top of the wafer. Vias in the first layer insulation expose the pads of N + K (where N and K are integers) desired usable cells in a first layer of metalization on the wafer. The pads are electrically connected through the vias to a second layer of metalization which is formed into individual conductors. The conductors are routed for effectively relocating the exposed pads of selected usable cells to desired positions defined by master pattern circuit locations including those usable cells whose actual positions are not in registry with the desired positions defined by master pattern circuit locations. The second layer of metallization and further includes ''''feed-under'''' conductor segments formed over specified non-used locations. A second layer of insulation has vias at standard or master pattern cell locations which expose the master pattern pads of the N + K cells to a top layer of metalization that includes a standard master pattern of interconnect lines which interconnect N of the cells into a functional circuit. The master pattern of metalization further includes pads associated with K extra cells which are located at scandard or master pattern cell locations. The extra cells can be utilized to replace faulty ones of the N interconnected cells by disabling, in the top layer of metalization, the interconnect lines associated with each faulty one of the N cells and connecting one of the extra cells to the disabled interconnect lines.
Inventors
- 👤 D Calhoun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:28
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10P; H10P95/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
434 words
An integrated circuit interconnection method for interconnecting operable ciruits on an integrated circuit wafer into an electrical function, in which the wafer is provided with a plurality of operable and inoperable circuits, the operable and inoperable circuits having random positions in a non-uniform distribution and having primary signal-connect means associated therewith at a first level of metalization, comprising the steps of: preparing a master pattern having predetermined circuit locations defining the desired positions of operable circuits on the wafer to be subjected to masking processes utilizing standardized mask means common to all wafers to be similarly processed into the electrical function; testing the plurality of operable and inoperable circuits to determine actual positions of operable and inoperable circuits; comparing the actual positions of the tested operable circuits to the desired positions as determined by the master pattern; selecting operable ciRcuits from any of the tested operable circuits irrespective of their position and distribution on the wafer, the number of selected operable circuits exceeding the number of operable circuits required to perform the electrical function, the number of selected operable circuits including a first group equalling the number of the predetermined circuit locations and a second group for use as additional repair circuits for any subsequently tested malfunctioning circuits of the first group; electrically coupling the primary signal-connect means of each of the first group of the selected operable circuits, including those first group operable circuits whose actual positions do not correspond to their desired positions, to sites of secondary signal-connect means situated at the desired positions, whereby each of the first group of the selected operable circuits are terminated in the secondary signalconnect means and in the desired positions corresponding to the predetermined circuit locations of the master pattern; electrically coupling the secondary signal connect means by use of the masking processes and the strandardized mask means to interconnect at a subsequent metallization level the first group of the selected operable circuits into an interconnection scheme, whereby the circuits in the wafer may be connected into the electrical function by use of the standardized mask means regardless of their actual positions on the wafer; electrically coupling the primary signal-connect means of each of the second group of the selected operable circuits to the subsequent metallization level; testing the first group of the selected operable circuits at the subsequent metallization level and electrically isolating any malfunctioning ones of the first group of the selected operable circuits; and electrically coupling any of the second group of the operable circuits previously brought to the subsequent metallization level in place of the malfunctioning ones of the first group.
Claim 2
Dependent Claim
434 words
An integrated circuit interconnection method for interconnecting operable ciruits on an integrated circuit wafer into an electrical function, in which the wafer is provided with a plurality of operable and inoperable circuits, the operable and inoperable circuits having random positions in a non-uniform distribution and having primary signal-connect means associated therewith at a first level of metalization, comprising the steps of: preparing a master pattern having predetermined circuit locations defining the desired positions of operable circuits on the wafer to be subjected to masking processes utilizing standardized mask means common to all wafers to be similarly processed into the electrical function; testing the plurality of operable and inoperable circuits to determine actual positions of operable and inoperable circuits; comparing the actual positions of the tested operable circuits to the desired positions as determined by the master pattern; selecting operable ciRcuits from any of the tested operable circuits irrespective of their position and distribution on the wafer, the number of selected operable circuits exceeding the number of operable circuits required to perform the electrical function, the number of selected operable circuits including a first group equalling the number of the predetermined circuit locations and a second group for use as additional repair circuits for any subsequently tested malfunctioning circuits of the first group; electrically coupling the primary signal-connect means of each of the first group of the selected operable circuits, including those first group operable circuits whose actual positions do not correspond to their desired positions, to sites of secondary signal-connect means situated at the desired positions, whereby each of the first group of the selected operable circuits are terminated in the secondary signalconnect means and in the desired positions corresponding to the predetermined circuit locations of the master pattern; electrically coupling the secondary signal connect means by use of the masking processes and the strandardized mask means to interconnect at a subsequent metallization level the first group of the selected operable circuits into an interconnection scheme, whereby the circuits in the wafer may be connected into the electrical function by use of the standardized mask means regardless of their actual positions on the wafer; electrically coupling the primary signal-connect means of each of the second group of the selected operable circuits to the subsequent metallization level; testing the first group of the selected operable circuits at the subsequent metallization level and electrically isolating any malfunctioning ones of the first group of the selected operable circuits; and electrically coupling any of the second group of the operable circuits previously brought to the subsequent metallization level in place of the malfunctioning ones of the first group.
Claim 3
Dependent Claim
123 words
The method of claim 1 wherein said first-mentioned routing step further comprises the steps of: electrically isolating each of the inoperable circuits, including each of the inoperable circuits coinciding with any ones of the desired positions defined by the predetermined circuit locations and electrically isolating each of the unselected operable circuits; exposing the primary signal-connect means of each of the first group of the selected operable circuits by masking and insulation material removal means; and routing electrical conduction means from the exposed primary signal-connect means to the sites of the secondary signal-connect means, whereby some of the secondary signal-connect means at the sites of secondary signal-connect means are situated over or near a corresponding number of the inoperable circuits in electrical isolation therefrom.
Claim 4
Dependent Claim
54 words
The method of claim 1 for use with a plurality of the wafers wherein the master pattern is identical for all the wafers, and electrically coupling the primary signal-connect means of each of the first group of the selected operable circuits of each of the wafers to the sites of the secondary signal-connect means.
Claim 5
Dependent Claim
275 words
The method of claim 1 wherein said first-mentioned coupling step comprises the steps of: forming a first layer of photoresist material over the first level of metallization; exposing to light portions of the first photoresist layer overlaying the primary signal-connect means of the selected operable circuits through masking means to form exposed portions and unexposed portions of the first photoresist layer, the exposed portions overlaying the primary signal-connect means of the selected operable circuits; removing the unexposed portions of the first photoresist layer; forming a layer of electrically insulating material over the circuits and the exposed photoresist portions of the first layer; heating the device to crack the insulating material over the first exposed photoresist portiOns; removing the first layer exposed photoresist portions and the cracked insulating material to expose the primary signal-connect means of the selected circuits through the thus formed feedthrough means in the insulating material; forming a layer of electrically conductive material on the insulating material and the exposed primary signal-connect means; forming a second layer of photoresist material on the layer of electrically conductive material; exposing portions of the second photoresist layer in a pattern of interconnect lines extending from the exposed primary signal-connect means to the sites of the secondary signal-connect means to form exposed and unexposed portions of the second photoresist layer; removing the second layer unexposed photoresist portions to expose portions of the conductive material; removing the exposed portions of the conductive material; and removing the exposed photoresist portions, leaving the conductive material in the pattern of interconnect lines, extending from the primary signal-connect means of the selected operable circuits to the sites of the secondary signal-connect means.
Claim 6
Dependent Claim
499 words
An integrated circuit interconnection method for use with a plurality of integrated circuit wafers, each capable of performing the same electrical function, each of the wafers having a plurality of operable and inoperable circuits in random positions of a non-uniform distribution, each of the circuits having primary signal-connect means associated therewith in a first level of metallization, comprising the steps of: preparing a master pattern having predetermined circuit locations identical for each and every one of the wafers, the predetermined circuit locations defining desired identical positions of operable circuits to be subjected to masking processes utilizing standardized mask means, the number of the desired positions of operable circuits exceeding the number of the operable circuits required to perform the electrical function; testing the plurality of operable and inoperable circuits of each of the wafers to determine actual positions of operable circuits on each of the wafers; for each of the wafers, comparing the actual positions of the tested operable circuits to the desired positions as determined by the master pattern; for each of the wafers, selecting operable circuits from any of the tested operable circuits irrespective of their position and distribution on individual ones of the wafers, the number of the selected operable circuits exceeding the number of operable circuits required to perform the electrical function; for each of the wafers, electrically insulating the operable and inoperable circuits and the primary signal-connect means from one another to form a first insulation layer over the primary signal-connect means, with feedthrough means in the first insulation layer opening to the primary signal-connect means of the selected operable circuits; for each of the wafers, electrically routing the primary signal-connect means of each of the selected operable circuits, including those operable circuits whose actual positions do not correspond to their desired positions, through the feedthrough means to sites of the secondary signal-connect means of each of the selected operable circuits and thereby terminating a number of the selected operable circuits in the desired identical positions sufficient in number corresponding to the predetermined circuit locations of the master pattern; further electrically routing and interconnecting the secondary signal-connect means on individual ones of the wafers to positions of further signal-connect means to integrate individual ones of the wafers into an interconnection scheme capable of performing the same electrical function by the masking processes and standardized mask means; testing the plurality of selected circuits of each of the wafers to identify malfunctioning selected operable circuits or routings after any of the elecTrically routing steps; electrically coupling the secondary signal-connect means or the further signal-connect means to the primary signal-connect means of any others of the operable circuits not previously utilized in the interconnection scheme in place of malfunctioning ones of the selected operable circuits and the coupling means; and electrically isolating the malfunctioning ones of the selected operable circuits and their routings, and the remaining ones of the selected operable circuits in excess of the number of the operable circuits required to perform the electrical function.
Claim 7
Dependent Claim
499 words
An integrated circuit interconnection method for use with a plurality of integrated circuit wafers, each capable of performing the same electrical function, each of the wafers having a plurality of operable and inoperable circuits in random positions of a non-uniform distribution, each of the circuits having primary signal-connect means associated therewith in a first level of metallization, comprising the steps of: preparing a master pattern having predetermined circuit locations identical for each and every one of the wafers, the predetermined circuit locations defining desired identical positions of operable circuits to be subjected to masking processes utilizing standardized mask means, the number of the desired positions of operable circuits exceeding the number of the operable circuits required to perform the electrical function; testing the plurality of operable and inoperable circuits of each of the wafers to determine actual positions of operable circuits on each of the wafers; for each of the wafers, comparing the actual positions of the tested operable circuits to the desired positions as determined by the master pattern; for each of the wafers, selecting operable circuits from any of the tested operable circuits irrespective of their position and distribution on individual ones of the wafers, the number of the selected operable circuits exceeding the number of operable circuits required to perform the electrical function; for each of the wafers, electrically insulating the operable and inoperable circuits and the primary signal-connect means from one another to form a first insulation layer over the primary signal-connect means, with feedthrough means in the first insulation layer opening to the primary signal-connect means of the selected operable circuits; for each of the wafers, electrically routing the primary signal-connect means of each of the selected operable circuits, including those operable circuits whose actual positions do not correspond to their desired positions, through the feedthrough means to sites of the secondary signal-connect means of each of the selected operable circuits and thereby terminating a number of the selected operable circuits in the desired identical positions sufficient in number corresponding to the predetermined circuit locations of the master pattern; further electrically routing and interconnecting the secondary signal-connect means on individual ones of the wafers to positions of further signal-connect means to integrate individual ones of the wafers into an interconnection scheme capable of performing the same electrical function by the masking processes and standardized mask means; testing the plurality of selected circuits of each of the wafers to identify malfunctioning selected operable circuits or routings after any of the elecTrically routing steps; electrically coupling the secondary signal-connect means or the further signal-connect means to the primary signal-connect means of any others of the operable circuits not previously utilized in the interconnection scheme in place of malfunctioning ones of the selected operable circuits and the coupling means; and electrically isolating the malfunctioning ones of the selected operable circuits and their routings, and the remaining ones of the selected operable circuits in excess of the number of the operable circuits required to perform the electrical function.
Claim 8
Dependent Claim
39 words
A method as in claim 1 further including the step of forming the master pattern of the predetermined circuit locations for the first group in accordance with the expected density of the selected operable circuits for all the wafers.
Claim 9
Independent Claim
287 words
A method of repairing a multi-level complex integrated circuit of the type including a wafer having a plurality of cells thereon, each cell having signal connects associated therewith in a layer of metaliztion on the wafer surface, comprising the steps of: predetermining cell locations in a master pattern to define desired positions of usable cells to be processed by standardized masking means having standard opening means therein; testing the cells to determine actual positions of usable cells; comparing the actual positions of the usable cells to the desired positions defined by the cell locations; electrically routing the signal connects of N usable cells in a group of N + K (where N and K are integers) usable cells to the desired positions defined by the master pattern and common to all wafers to be similarly processed in a subsequent layer of metalization; electrically interconnecting the signal connects of the N cells at the desired positions by the standardized masking means into a functional circuit type at a further layer of metalization subsequent to the first-mentioned layer of metalization and forming signal connects for K of the usable cells at the further layer of metalization; electrically testing the functions of the interconnected N cells for faulty ones of the N cells; electrically isolating the faulty ones of the N cells from the remaining N cells by open-circuiting the signal interconnects in the further layer of metalization associated with faulty ones of the N cells; and interconnecting the signal connects of corresponding ones of the K cells to the open-circuited signal interconnects associated with the isolated N cells to interconnect the corresponding ones of the K cells into circuit relationship with the remaining ones of the interconnected N cells.
Claim 10
Independent Claim
287 words
A method of repairing a multi-level complex integrated circuit of the type including a wafer having a plurality of cells thereon, each cell having signal connects associated therewith in a layer of metaliztion on the wafer surface, comprising the steps of: predetermining cell locations in a master pattern to define desired positions of usable cells to be processed by standardized masking means having standard opening means therein; testing the cells to determine actual positions of usable cells; comparing the actual positions of the usable cells to the desired positions defined by the cell locations; electrically routing the signal connects of N usable cells in a group of N + K (where N and K are integers) usable cells to the desired positions defined by the master pattern and common to all wafers to be similarly processed in a subsequent layer of metalization; electrically interconnecting the signal connects of the N cells at the desired positions by the standardized masking means into a functional circuit type at a further layer of metalization subsequent to the first-mentioned layer of metalization and forming signal connects for K of the usable cells at the further layer of metalization; electrically testing the functions of the interconnected N cells for faulty ones of the N cells; electrically isolating the faulty ones of the N cells from the remaining N cells by open-circuiting the signal interconnects in the further layer of metalization associated with faulty ones of the N cells; and interconnecting the signal connects of corresponding ones of the K cells to the open-circuited signal interconnects associated with the isolated N cells to interconnect the corresponding ones of the K cells into circuit relationship with the remaining ones of the interconnected N cells.
Claim 11
Dependent Claim
35 words
The method of claim 7 further comprising the step of routing all usable signal connects associated with the N + K cells to the top level of metalization through vias in a layer of insulation.
Claim 12
Dependent Claim
50 words
The method of claim 7 further comprising the steps of routing the second layer of metalization in the master pattern of conductors that is common to a plurality of wafers having a non-standard yield pattern and routing the signal connects of usable cells to desired positions defined by the locations.
References Cited (Backward Citations)
GB1117579A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-03-11 | 1977-09-10 | 1978-03-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-03-11 | 1981-09-10 | 1982-03-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-03-11 | 1985-09-10 | 1986-03-12 | $7700.00 | Window Closed / Lapsed |