US4841482A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Leakage verification for flash EPROM
Assignee: Intel Corp
•
Filing: 1988-02-17
•
Granted: 1989-06-20
•
Expires: 2008-02-17
Abstract
Abstract A circuit and method for verifying leakage in a flash EPROM/EEPROM memory cell which is fabricated on a silicon substrate having floating gate. A word line coupled to the control gate of the memory cell is typically at ground potential, but during a test mode a positive voltage is placed on the control gate and leakage current at the drain is measured. A good cell will typically have zero or negligible drain leakage current, however, a cell which is susceptible to being overerased will exhibit appreciable leakage current. A circuit is implemented on the chip with the memory for switching a positive voltage onto the word line during the test mode.
Inventors
- 👤 Jerry A. Kreifels
- 👤 George Hoekstra
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:57
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/344; G11C16/345; G11C29/00; G11C29/02; G11C29/025; G11C29/04; G11C29/50; G11C16/04; G11C2029/5006
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
139 words
An electrically erasable and electrically programmable read-only memory fabricated on a silicon substrate and employing a plurality of memory cells each of which has a floating gate, an improvement for verifying leakage current from said memory cells comprising: circuit means incorporated on said substrate for providing a first reference voltage and a second reference voltage onto word lines coupled to a control gate of each of said memory cells, wherein said first reference level is coupled to said word line under normal operation, but during a test verification mode, said circuit means provides said second reference level onto said word line such that a current measurement device coupled to drains of said memory cells measures leakage current from said cells, said leakage current being above a predetermined value if a given cell is leaky and susceptible to being overerased.
Claim 2
Dependent Claim
139 words
An electrically erasable and electrically programmable read-only memory fabricated on a silicon substrate and employing a plurality of memory cells each of which has a floating gate, an improvement for verifying leakage current from said memory cells comprising: circuit means incorporated on said substrate for providing a first reference voltage and a second reference voltage onto word lines coupled to a control gate of each of said memory cells, wherein said first reference level is coupled to said word line under normal operation, but during a test verification mode, said circuit means provides said second reference level onto said word line such that a current measurement device coupled to drains of said memory cells measures leakage current from said cells, said leakage current being above a predetermined value if a given cell is leaky and susceptible to being overerased.
Claim 3
Dependent Claim
12 words
The improvement of claim 1, wherein said first reference level is ground.
Claim 4
Dependent Claim
14 words
The improvement of claim 1, wherein said second reference level is approximately 0-3.0 volts.
Claim 5
Dependent Claim
193 words
An electrically erasable and electrically programmable read-only memory fabricated on a silicon substrate and having a plurality of memory cells each of which has a floating gate, an improvement for verifying susceptibility of said memory cells to an overerase condition by measuring leakage current from said drain of memory device comprising: first circuit means coupled to provide a ground potential to word lines which are coupled to control gates of said memory cell under normal operation, but switches a non-zero voltage onto said word lines during a test mode, such that said non-zero voltage biases said memory cell and causes cells which are susceptible to an overerase condition to generate a predetermined leakage current; said circuit comprising a first, second and third transistors; said first, second and third transistors coupled in series between a supply voltage and ground; said ground and non-zero voltage being derived at junction of said second and third transistors; such that at normal operation, said third transistor is switched on to couple ground potential to said word lines and during said test mode, said first and second transistors are switched on to couple said voltage to said word lines.
Claim 6
Dependent Claim
193 words
An electrically erasable and electrically programmable read-only memory fabricated on a silicon substrate and having a plurality of memory cells each of which has a floating gate, an improvement for verifying susceptibility of said memory cells to an overerase condition by measuring leakage current from said drain of memory device comprising: first circuit means coupled to provide a ground potential to word lines which are coupled to control gates of said memory cell under normal operation, but switches a non-zero voltage onto said word lines during a test mode, such that said non-zero voltage biases said memory cell and causes cells which are susceptible to an overerase condition to generate a predetermined leakage current; said circuit comprising a first, second and third transistors; said first, second and third transistors coupled in series between a supply voltage and ground; said ground and non-zero voltage being derived at junction of said second and third transistors; such that at normal operation, said third transistor is switched on to couple ground potential to said word lines and during said test mode, said first and second transistors are switched on to couple said voltage to said word lines.
Claim 7
Dependent Claim
15 words
The improvement of claim 4, wherein said first, second and third transistors are n-channel transistors.
Claim 8
Dependent Claim
16 words
The improvement of claim 5, wherein said nonzero voltage is variable between 0 and 3.0 volts.
References Cited (Backward Citations)
US4779272A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-19 | 1992-12-19 | 1993-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-19 | 1996-12-19 | 1997-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-19 | 2000-12-19 | 2001-06-20 | $7700.00 | Window Closed / Lapsed |