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US5701496A
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Multi-processor computer system with interrupt controllers providing remote reading
Assignee: Intel Corp
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Filing: 1996-09-17
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Granted: 1997-12-23
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Expires: 2016-09-17
Abstract
Abstract A multi-processor programmable interrupt controller system that includes: an I/O interrupt controller for receiving interrupt requests from an I/O subsystem; multiple processor interrupt controllers, each associated with a specific processor for dispensing of accepted interrupts; and an interrupt controller bus primarily for the transmission of interrupt requests between interrupt controller units and for bus and priority arbitration, using a standard message format and arbitration protocol. The system is implemented, in part, by incorporating the processor interrupt controller with its associated processor into a single integrated circuit. The common system bus which normally carries all system traffic is not used for interrupt request messages. The interrupt controller bus is used for this purpose and thus results in a more efficient system by relieving the system bus of interrupt service requests and the related interrupt request traffic.
Inventors
- 👤 P. K. Nizar
- 👤 David Carson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 18:56
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F9/4818; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26; G06F15/00; G06F15/16; G06F15/163; G06F15/17
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
136 words
A multi-processor (MP) system comprising: a system bus; a plurality of processors that communicate on the system bus; an interrupt bus; a first interrupt controller coupled to the interrupt bus and to a first processor, the first interrupt controller having a control register that stores a value which controls acceptance of an interrupt request; a second interrupt controller coupled to the interrupt bus and to a second processor, the second interrupt controller including logic that broadcasts a remote read message on the interrupt bus that requests the value stored in the control register from the first interrupt controller; and the first interrupt controller further including logic that supplies the value of the control register on the interrupt bus in response to the remote read message, the second interrupt controller receiving the value across the interrupt bus.
Claim 2
Dependent Claim
136 words
A multi-processor (MP) system comprising: a system bus; a plurality of processors that communicate on the system bus; an interrupt bus; a first interrupt controller coupled to the interrupt bus and to a first processor, the first interrupt controller having a control register that stores a value which controls acceptance of an interrupt request; a second interrupt controller coupled to the interrupt bus and to a second processor, the second interrupt controller including logic that broadcasts a remote read message on the interrupt bus that requests the value stored in the control register from the first interrupt controller; and the first interrupt controller further including logic that supplies the value of the control register on the interrupt bus in response to the remote read message, the second interrupt controller receiving the value across the interrupt bus.
Claim 3
Dependent Claim
49 words
The MP system of claim 1 wherein the value is supplied by the first interrupt controller in a set of bus cycles, in a subsequent bus cycle the second interrupt controller reading a remote read status field in an interrupt command register to determine the validity of the value.
Claim 4
Dependent Claim
18 words
The MP system of claim 1 wherein the value comprises a priority indication of the first interrupt controller.
Claim 5
Dependent Claim
24 words
The MP system of claim 3 wherein the first interrupt controller includes arbitration circuitry that arbitrates for the interrupt bus based on the value.
Claim 6
Dependent Claim
127 words
An interrupt controller for coupling to an interrupt bus in a multi-processor (MP) computer system which includes a system bus and a plurality of processors that communicate on the system bus, the interrupt controller comprising: a plurality of registers that control acceptance of interrupts from the interrupt bus for service by an associated processor, the plurality of registers including a control register that stores a value, and an address register that stores a unique identification (ID); and logic that responds to a remote read message from a requesting agent on the interrupt bus by supplying the value on the interrupt bus to the requesting agent, the remote read message including a destination address, and the logic being responsive when the destination address corresponds to the unique ID.
Claim 7
Dependent Claim
127 words
An interrupt controller for coupling to an interrupt bus in a multi-processor (MP) computer system which includes a system bus and a plurality of processors that communicate on the system bus, the interrupt controller comprising: a plurality of registers that control acceptance of interrupts from the interrupt bus for service by an associated processor, the plurality of registers including a control register that stores a value, and an address register that stores a unique identification (ID); and logic that responds to a remote read message from a requesting agent on the interrupt bus by supplying the value on the interrupt bus to the requesting agent, the remote read message including a destination address, and the logic being responsive when the destination address corresponds to the unique ID.
Claim 8
Dependent Claim
18 words
The interrupt controller of claim 5 wherein the logic includes arbitration circuitry that arbitrates for the interrupt bus.
Claim 9
Dependent Claim
31 words
The interrupt controller of claim 5 wherein the plurality of registers includes an interrupt request register having a bit that is set when an interrupt is accepted by the interrupt controller.
Claim 10
Dependent Claim
25 words
The interrupt controller of claim 5 further comprising status monitor circuitry that indicates when the message is in progress, and a validity of the message.
Claim 11
Independent Claim
119 words
A method of operation in a computer system that includes a plurality of processors that communicate via a system bus, the processors having associated interrupt controllers coupled via an interrupt bus, the method comprising the steps of: (a) broadcasting, by a first interrupt controller associated with a first processor, a remote read request on the interrupt bus, the remote read request including a destination identification of a second interrupt controller; (b) receiving, by a second interrupt controller, associated with a second processor, the remote read request; (c) supplying, by the second interrupt controller, a control register value on the interrupt bus responsive to the remote read request; and (d) storing, by the first interrupt controller, the control register value.
Claim 12
Independent Claim
119 words
A method of operation in a computer system that includes a plurality of processors that communicate via a system bus, the processors having associated interrupt controllers coupled via an interrupt bus, the method comprising the steps of: (a) broadcasting, by a first interrupt controller associated with a first processor, a remote read request on the interrupt bus, the remote read request including a destination identification of a second interrupt controller; (b) receiving, by a second interrupt controller, associated with a second processor, the remote read request; (c) supplying, by the second interrupt controller, a control register value on the interrupt bus responsive to the remote read request; and (d) storing, by the first interrupt controller, the control register value.
Claim 13
Dependent Claim
19 words
The method of claim 9 wherein the control register value comprises an identification (ID) of the first interrupt controller.
Claim 14
Dependent Claim
20 words
The method of claim 9 further comprising the step of: providing the first processor with a remote read status signal.
References Cited (Backward Citations)
GB1357576A
Cited
US3905025A
Cited
US3895353A
Cited
US3812463A
Cited
US4394730A
Cited
US4209838A
Cited
US4268904A
Cited
US4250546A
Cited
US4482954A
Cited
US4271468A
Cited
US4402040A
Cited
US4484264A
Cited
US4420806A
Cited
US4435780A
Cited
US4495569A
Cited
US4621342A
Cited
US5083261A
Cited
US4654820A
Cited
US4868742A
Cited
US4648029A
Cited
US4799148A
Cited
US5067071A
Cited
US4788639A
Cited
US4796176A
Cited
US4930070A
Cited
US4833598A
Cited
US4839800A
Cited
US4860196A
Cited
US4805096A
Cited
US4866664A
Cited
US5428794A
Cited
US4953072A
Cited
US4980854A
Cited
US5146597A
Cited
US5134706A
Cited
US4914580A
Cited
US4920486A
Cited
US4903270A
Cited
US5099414A
Cited
US5218703A
Cited
US5101497A
Cited
US5274767A
Cited
US5155853A
Cited
US5210828A
Cited
US5060139A
Cited
US5283869A
Cited
US5201051A
Cited
US5261107A
Cited
US5325536A
Cited
US5193187A
Cited
US5123094A
Cited
US5179707A
Cited
US5125093A
Cited
US5282272A
Cited
US5283904A
Cited
US5410710A
Cited
US5265215A
Cited
US5276690A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-22 | 2001-06-23 | 2001-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-22 | 2005-06-23 | 2005-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-22 | 2009-06-23 | 2009-12-23 | $7700.00 | Window Closed / Lapsed |