Interrupt distribution scheme for a computer bus

Claim 1

A method for having a first processor request a second processor of a computer system to perform an interrupt operation, wherein the computer system includes a plurality of processors including the first processor and the second processor, wherein the plurality of processors are coupled to a bus, wherein each of the plurality of processors has a processing priority based on a predetermined priority of a program being executed on the respective one of the plurality of processors, comprising the steps of: (a) generating in the first processor an interrupt request with an interrupt priority for the second processor; (b) sending the interrupt request to the second processor via the bus, wherein the second processor performs the interrupt operation if the interrupt request has an interrupt priority higher than the processing priority of the second processor, wherein if the second processor accepts the interrupt request, the second processor returns an acknowledgement to the first processor via the bus, wherein the second processor does not accept the interrupt request and does not return the acknowledgement to the first processor if the interrupt priority of the interrupt request is not higher than the processing priority of the second processor; (c) determining if the acknowledgement is received in the first processor; (d) if the acknowledgement is not received, then (1) resending the interrupt request from the first processor to the second processor with the interrupt priority; (2) determining if the acknowledgement is received in the first processor; (3) if the acknowledgement is still not received, then repeating steps (d)(1) through (d)(2) if the steps (d)(1) through (d)(2) have been repeated fewer than X times, wherein X is a nonzero positive integer; (e) if the acknowledgement is still not received and if the steps (d)(1) through (d)(2) have been repeated the X times, then (1) increasing the interrupt priority of the interrupt request to an adjacent higher level in the first processor if the interrupt priority has not reached a highest level; (2) resending the interrupt request with the increased interrupt priority from the first processor to the second processor; (3) determining if the acknowledgement is received in the first processor; (4) if the acknowledgement is still not received, then repeating steps (e)(2) through (e)(3) if the steps (e)(2) through (e)(3) have been repeated fewer than Y times, wherein Y is a nonzero positive integer; (f) if the acknowledgement is still not received and if the steps (e)(2) through (e)(3) have been repeated the Y times, then repeating steps (e)(1) through (e)(4) until it has been determined that the first processor has received the acknowledgement; and (g) if the acknowledgement is received in the first processor, then stopping resending the interrupt request to the second processor.

Claim 2

A method for having a first processor request a second processor of a computer system to perform an interrupt operation, wherein the computer system includes a plurality of processors including the first processor and the second processor, wherein the plurality of processors are coupled to a bus, wherein each of the plurality of processors has a processing priority based on a predetermined priority of a program being executed on the respective one of the plurality of processors, comprising the steps of: (a) generating in the first processor an interrupt request with an interrupt priority for the second processor; (b) sending the interrupt request to the second processor via the bus, wherein the second processor performs the interrupt operation if the interrupt request has an interrupt priority higher than the processing priority of the second processor, wherein if the second processor accepts the interrupt request, the second processor returns an acknowledgement to the first processor via the bus, wherein the second processor does not accept the interrupt request and does not return the acknowledgement to the first processor if the interrupt priority of the interrupt request is not higher than the processing priority of the second processor; (c) determining if the acknowledgement is received in the first processor; (d) if the acknowledgement is not received, then (1) resending the interrupt request from the first processor to the second processor with the interrupt priority; (2) determining if the acknowledgement is received in the first processor; (3) if the acknowledgement is still not received, then repeating steps (d)(1) through (d)(2) if the steps (d)(1) through (d)(2) have been repeated fewer than X times, wherein X is a nonzero positive integer; (e) if the acknowledgement is still not received and if the steps (d)(1) through (d)(2) have been repeated the X times, then (1) increasing the interrupt priority of the interrupt request to an adjacent higher level in the first processor if the interrupt priority has not reached a highest level; (2) resending the interrupt request with the increased interrupt priority from the first processor to the second processor; (3) determining if the acknowledgement is received in the first processor; (4) if the acknowledgement is still not received, then repeating steps (e)(2) through (e)(3) if the steps (e)(2) through (e)(3) have been repeated fewer than Y times, wherein Y is a nonzero positive integer; (f) if the acknowledgement is still not received and if the steps (e)(2) through (e)(3) have been repeated the Y times, then repeating steps (e)(1) through (e)(4) until it has been determined that the first processor has received the acknowledgement; and (g) if the acknowledgement is received in the first processor, then stopping resending the interrupt request to the second processor.