Abstract A distributed function processing system utilizing a conventional microprocessor operated as a text processor in combination with a plurality of other autonomous processing devices arranged to operate in a coherent processing system. One of the autonomous processors which is a memory control processor serves to periodically overlay a random access accelerator memory with the contents of a main memory system and concurrently resolves conflicts among various other autonomous memory service requests. This processor, therefore, accommodates the data rates of the main memory. The other processor is a display processor which generates signals to a video display system to provide a visual interface to the user and is therefore tied to the video rate. Accordingly, the processing burden is distributed within processors entailing differing rates operating autonomously. The memory control processor resolves and accommodates all of the memory service requests in the system and also performs control operations to support high speed I/O devices. Logic is provided to handle the other interrupts. Also, there is page mapping for context switching of a reference page and repeating logic for decoupling this processor from the other processors. This arrangement allows convenient expansion into plural work stations each sharing a common memory.
Inventors
👤 David Cronshaw
👤 Jack E. Shemer
👤 William D. Turner
👤 David Hartke
👤 James R. Keddy
👤 Wilbur E. DuVall
👤 Warren M. Sterling
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-10-25 06:23
CPC Classifications
G; G06; G06F; G06F40/00; G06F40/10
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
316 words
A data processing system adapted for text editing comprising: an external bus system; a text processor including a memory portion, said text processor being coupled to said bus system, said text processor receiving input signals from said bus system and producing at a first cyclic rate predetermined command signals in response to said input signals; a semi-autonomous memory control processor coupled to said bus system, said memory control processor including a main memory and an accelerator memory for storing data signals and instruction signals, said main memory periodically advancing at a second cyclic rate data therefrom to said accelerator memory in response to receipt by said memory control processor of selected ones of said command signals; isolating means connected between said text processor and said bus system and responsive to signals received from said memory control processor for decoupling said text processor from the communications on said bus system during the times when said memory control processor is advancing said data signals and instruction signals from said main memory of said memory control processor to said accelerator memory of said memory control processor; a semi-autonomous display processor coupled to said bus system, said display processor including a video display means and a list of memory means independent of said memory portion of said text processor, said list memory having signals stored therein and being responsive to selected other ones of said command signals and said video display means being rendered cyclically operative independent of said selected other ones of said command signals for producing images of characters and graphics at a third cyclic rate according to the signals stored in said list memory; and at least one data input device coupled to said bus system, said data input device being coupled through said external bus system to said memory portion of said text processor and utilizing as its memory said memory portion of said text processor.
Claim 2
Dependent Claim
316 words
A data processing system adapted for text editing comprising: an external bus system; a text processor including a memory portion, said text processor being coupled to said bus system, said text processor receiving input signals from said bus system and producing at a first cyclic rate predetermined command signals in response to said input signals; a semi-autonomous memory control processor coupled to said bus system, said memory control processor including a main memory and an accelerator memory for storing data signals and instruction signals, said main memory periodically advancing at a second cyclic rate data therefrom to said accelerator memory in response to receipt by said memory control processor of selected ones of said command signals; isolating means connected between said text processor and said bus system and responsive to signals received from said memory control processor for decoupling said text processor from the communications on said bus system during the times when said memory control processor is advancing said data signals and instruction signals from said main memory of said memory control processor to said accelerator memory of said memory control processor; a semi-autonomous display processor coupled to said bus system, said display processor including a video display means and a list of memory means independent of said memory portion of said text processor, said list memory having signals stored therein and being responsive to selected other ones of said command signals and said video display means being rendered cyclically operative independent of said selected other ones of said command signals for producing images of characters and graphics at a third cyclic rate according to the signals stored in said list memory; and at least one data input device coupled to said bus system, said data input device being coupled through said external bus system to said memory portion of said text processor and utilizing as its memory said memory portion of said text processor.