Apparatus for interrupt detection and arbitration

Claim 1

An apparatus for interrupt detection and arbitration in a system which includes a plurality of circuit modules connected to each other by a common bus, said apparatus comprising: (a) means provided in at lest one of the circuit modules for detecting an interrupt signal on the common bus and generating an interrupt transfer cycle; (b) means provided in the circuit modules for applying the interrupt signal to the common bus, said interrupt signal being generated in at least one of the circuit modules; (c) means responsive to the start of the interrupt transfer cycle for dividing the interrupt transfer cycle into an interrupt destination notifying cycle and a succeeding interrupt source notifying cycle; (d) means responsive to the interrupt destination notifying cycle for applying information identifying at least one destination circuit module on the common bus; (e) means for arbitrating the information applied on the common bus if a plurality of destination circuit modules are identified, and for selecting a single one of them as an arbitrated destination circuit module; (f) means responsive to the interrupt source notifying cycle for applying on the common bus information identifying at least one interrupt source circuit module that identified the arbitrated destination circuit module during the interrupt destination notifying cycle; and (g) means provided in the arbitrated destination circuit module for accepting the information identifying the at least one interrupt source circuit module.

Claim 2

An apparatus for interrupt detection and arbitration in a system which includes a plurality of circuit modules connected to each other by a common bus, said apparatus comprising: (a) means provided in at lest one of the circuit modules for detecting an interrupt signal on the common bus and generating an interrupt transfer cycle; (b) means provided in the circuit modules for applying the interrupt signal to the common bus, said interrupt signal being generated in at least one of the circuit modules; (c) means responsive to the start of the interrupt transfer cycle for dividing the interrupt transfer cycle into an interrupt destination notifying cycle and a succeeding interrupt source notifying cycle; (d) means responsive to the interrupt destination notifying cycle for applying information identifying at least one destination circuit module on the common bus; (e) means for arbitrating the information applied on the common bus if a plurality of destination circuit modules are identified, and for selecting a single one of them as an arbitrated destination circuit module; (f) means responsive to the interrupt source notifying cycle for applying on the common bus information identifying at least one interrupt source circuit module that identified the arbitrated destination circuit module during the interrupt destination notifying cycle; and (g) means provided in the arbitrated destination circuit module for accepting the information identifying the at least one interrupt source circuit module.

Claim 3

An apparatus for interrupt detection and arbitration in a system which includes a CPU module and a plurality of additional circuit modules connected to each other by a common bus, said apparatus comprising: (a) a plurality of interrupt detector/arbiter circuits, each interrupt detector/arbiter circuit being provided in a respective one of the additional circuit modules and including (a-1) means for transferring an interrupt signal generated by the respective additional circuit module to the common bus; (a-2) means for driving an assigned line in the common bus in response to a first control signal on the common bus, the assigned line corresponding to a signal which is generated by the respective additional circuit module and which identifies another additional circuit module as an interrupt destination circuit module; (a-3) means for latching the status of the common bus to detect the driven lines and the corresponding interrupt destination circuit modules, said latching means further arbitrating the detected interrupt destination circuit modules and outputting an arbitration result which identifies a selected interrupt destination circuit module; (a-4) means for comparing the result of the arbitration and said signal which is generated by the respective additional circuit module and which identifies another additional circuit module as an interrupt destination circuit module, said comparing means outputting a second control signal if the arbitration result and said signal which is generated by the respective additional circuit module and which identifies another additional circuit module as an interrupt destination circuit module are the same; (a-5) means responsive to the second control signal for driving a signal line among the common bus corresponding to a a signal identifying the respective additional circuit module; (a-6) means for comparing the signal identifying the respective additional circuit module and the result of the arbitration, said comparing means outputting a third control signal if the respective additional circuit module and the result of the arbitration are the same; and (a-7) means responsive to the third control signal for latching the status of the common bus to identify additional circuit modules which have made interrupts to the respective additional circuit module; and (b) a central controller circuit in the CPU module of the system, the central control circuit including means for detecting the interrupt signal on the common bus and generating the first control signal on the common bus in a predetermined interval.

Claim 4

An apparatus for interrupt detection and arbitration in a system which includes a CPU module and a plurality of additional circuit modules connected to each other by a common bus, said apparatus comprising: (a) a plurality of interrupt detector/arbiter circuits, each interrupt detector/arbiter circuit being provided in a respective one of the additional circuit modules and including (a-1) means for transferring an interrupt signal generated by the respective additional circuit module to the common bus; (a-2) means for driving an assigned line in the common bus in response to a first control signal on the common bus, the assigned line corresponding to a signal which is generated by the respective additional circuit module and which identifies another additional circuit module as an interrupt destination circuit module; (a-3) means for latching the status of the common bus to detect the driven lines and the corresponding interrupt destination circuit modules, said latching means further arbitrating the detected interrupt destination circuit modules and outputting an arbitration result which identifies a selected interrupt destination circuit module; (a-4) means for comparing the result of the arbitration and said signal which is generated by the respective additional circuit module and which identifies another additional circuit module as an interrupt destination circuit module, said comparing means outputting a second control signal if the arbitration result and said signal which is generated by the respective additional circuit module and which identifies another additional circuit module as an interrupt destination circuit module are the same; (a-5) means responsive to the second control signal for driving a signal line among the common bus corresponding to a a signal identifying the respective additional circuit module; (a-6) means for comparing the signal identifying the respective additional circuit module and the result of the arbitration, said comparing means outputting a third control signal if the respective additional circuit module and the result of the arbitration are the same; and (a-7) means responsive to the third control signal for latching the status of the common bus to identify additional circuit modules which have made interrupts to the respective additional circuit module; and (b) a central controller circuit in the CPU module of the system, the central control circuit including means for detecting the interrupt signal on the common bus and generating the first control signal on the common bus in a predetermined interval.

Claim 5

An apparatus for interrupt detection and arbitration in a system which includes a plurality of circuit modules connected to each other by a common bus, said apparatus comprising: (a) a plurality of interrupt detector/arbiter circuits, each interrupt detector/arbiter circuit being provided in a respective circuit module and including (a-1) means for transferring an interrupt signal generated by the respective circuit module to the common bus; (a-2) means for driving an assigned line in the common bus in response to a first control signal on the common bus, the assigned line corresponding to a signal which is generated by the respective circuit module and which identifies another circuit module as an interrupt destination circuit module; (a-3) means for latching the status of the common bus to detect the driven lines and the corresponding interrupt destination circuit modules, said latching means further arbitrating the detected interrupt destination circuit modules and outputting an arbitration result which identifies a selected interrupt destination circuit module; (a-4) means for comparing the result of the arbitration and said signal which is generated by the respective circuit module and which identifies another circuit module as an interrupt destination circuit module, said comparing means outputting a second control signal if the arbitration result and said signal which is generated by the respective circuit module and which identifies another circuit module as an interrupt destination circuit module are the same; (a-5) means responsive to the second control signal for driving a signal line among the common bus corresponding to a signal identifying the respective circuit module; (a-6) means for comparing the signal identifying the respective circuit module and the result of the arbitration, said comparing means outputting a third control signal if the respective circuit module and the result of the arbitration are the same; and (a-7) means responsive to the third control signal for latching the status of the common bus to identify circuit modules which have made interrupts to the respective circuit module; and (b) a central controller circuit provided in at least one of the circuit modules of the system, the central controller circuit including means for detecting the interrupt signal on the common bus and generating the first control signal on the common bus in a predetermined interval.

Claim 6

An apparatus for interrupt detection and arbitration in a system which includes a plurality of circuit modules connected to each other by a common bus, said apparatus comprising: (a) a plurality of interrupt detector/arbiter circuits, each interrupt detector/arbiter circuit being provided in a respective circuit module and including (a-1) means for transferring an interrupt signal generated by the respective circuit module to the common bus; (a-2) means for driving an assigned line in the common bus in response to a first control signal on the common bus, the assigned line corresponding to a signal which is generated by the respective circuit module and which identifies another circuit module as an interrupt destination circuit module; (a-3) means for latching the status of the common bus to detect the driven lines and the corresponding interrupt destination circuit modules, said latching means further arbitrating the detected interrupt destination circuit modules and outputting an arbitration result which identifies a selected interrupt destination circuit module; (a-4) means for comparing the result of the arbitration and said signal which is generated by the respective circuit module and which identifies another circuit module as an interrupt destination circuit module, said comparing means outputting a second control signal if the arbitration result and said signal which is generated by the respective circuit module and which identifies another circuit module as an interrupt destination circuit module are the same; (a-5) means responsive to the second control signal for driving a signal line among the common bus corresponding to a signal identifying the respective circuit module; (a-6) means for comparing the signal identifying the respective circuit module and the result of the arbitration, said comparing means outputting a third control signal if the respective circuit module and the result of the arbitration are the same; and (a-7) means responsive to the third control signal for latching the status of the common bus to identify circuit modules which have made interrupts to the respective circuit module; and (b) a central controller circuit provided in at least one of the circuit modules of the system, the central controller circuit including means for detecting the interrupt signal on the common bus and generating the first control signal on the common bus in a predetermined interval.