Processor interrupt pointer

Claim 2

In a multiprocessing system comprising a memory storing programs of instructions including an executive program, a first command arithmetic unit (CAUA) and a second command arithmetic unit (CAUB), an input/output access unit (IOAU), means for routing interrupt request signals from said IOAU selectively to either of said CAU''s or to said two CAU''s alternately, and comprising: processor interrupt pointer (PIP) register means coupled to said memory for receiving and storing an instruction defining which of a plurality of possible routes to a CAU the next incoming interrupt request signal is to take; first control means coupled to said memory and adapted to receive an instruction from said executive program stored in said memory for loading said PIP register with an instruction; and second control means responsive to the instruction stored in said PIP register to route the next executed interrupt request signal to a selected one of said first and second CAU''s.

Claim 3

In a multiprocessor system employing interrupt request signals and comprising a first command arithmetic unit (CAUA), a second command arithmetic unit (CAUB), an input/output access unit (IOAU), and decision means for producing instructions for determining to which CAU each received interrupt request signal is to be routed, a method for routing said interrupt request signals to the CAU determined by the instructions produced by said decision means and comprising the steps of: generating a first, second, third or fourth instruction for routing a received interrupt request signal respectively to the CAU which originated the activity resulting in the generation of the received interrupt request signal, to CAUA and CAUB alternately, to CAUA or to CAUB; loading the generated instruction into a storage register; decoding the loaded instruction; establishing a route to CAUA or CAUB for the next received interrupt request signal in accordance with the instruction loaded in said storage register; routing said next received interrupt request signal to CAUA or CAUB along the route established in accordance with the instruction stored in said storage register.

Claim 4

In a multiprocessor system employing interrupt request signals and comprising a first command arithmetic unit (CAUA), a second command arithmetic unit (CAUB), an input/output access unit (IOAU), and decision means for producing instructions for determining to which CAU each received interrupt request signal is to be routed, a method for routing said interrupt request signals to the CAU determined by the instructions produced by said decision means and comprising the steps of: generating a first, second, third or fourth instruction for routing a received interrupt request signal respectively to the CAU which originated the activity resulting in the generation of the received interrupt request signal, to CAUA and CAUB alternately, to CAUA or to CAUB; loading the generated instruction into a storage register; decoding the loaded instruction; establishing a route to CAUA or CAUB for the next received interrupt request signal in accordance with the instruction loaded in said storage register; routing said next received interrupt request signal to CAUA or CAUB along the route established in accordance with the instruction stored in said storage register.