US5325536A
Expired / Lapsed
US
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Linking microprocessor interrupts arranged by processing requirements into separate queues into one interrupt processing routine for execution as one routine
Assignee: Motorola Solutions Inc
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Filing: 1992-11-24
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Granted: 1994-06-28
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Expires: 2012-11-24
Abstract
Abstract Multiple interrupt request data is stored in a queue and handled by a single interrupt sub-routine to provide a batch handling capability to maximize the interrupt handling efficiency of a microprocessor. Events are organized into groups having a common interrupt handling requirement and a data storage queue is provided for each group. At least one data word is stored for each event requiring interrupt attention in a respective queue. An interrupt handling routine upon a single call handles all data words within a queue before exiting the interrupt handling routine.
Inventors
- 👤 Hungkun J. Chang
- 👤 John M. Kaczmarczk
- 👤 Richard E. White
- 👤 James D. McGrath
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 03:28
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F13/00; G06F13/14; G06F13/20; G06F13/24
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
123 words
A method for organizing and handling recurring microprocessor interrupts within a microprocessor based computing system comprising the steps of: organizing events into respective groups which have common interrupt handling requirements, each respective group having a different set of interrupt handling requirements; providing different interrupt handling routines for each group; providing a data storage queue for each group; storing at least one data word for each event requiring interrupt attention in its respective queue; linking together at least some of the different interrupt handling routines into a linked interrupt handling routine; and initiating the linked interrupt handling routine whereby each data word in each queue associated with the linked interrupt handling routine is serviced by the microprocessor before exiting the linked interrupt handling routine.
Claim 2
Independent Claim
123 words
A method for organizing and handling recurring microprocessor interrupts within a microprocessor based computing system comprising the steps of: organizing events into respective groups which have common interrupt handling requirements, each respective group having a different set of interrupt handling requirements; providing different interrupt handling routines for each group; providing a data storage queue for each group; storing at least one data word for each event requiring interrupt attention in its respective queue; linking together at least some of the different interrupt handling routines into a linked interrupt handling routine; and initiating the linked interrupt handling routine whereby each data word in each queue associated with the linked interrupt handling routine is serviced by the microprocessor before exiting the linked interrupt handling routine.
Claim 3
Dependent Claim
30 words
The method according to claim 1 wherein said step of linking at least some of the different interrupt handling routines comprises the step of identifying the queues to be serviced.
Claim 4
Dependent Claim
48 words
The method according to claim 2 wherein said step of identifying the queues to be serviced includes the step of designating each queue with unique queue identification data and sending the queue identification data of each queue having at least one data word stored therein to the microprocessor.
Claim 5
Dependent Claim
33 words
The method according to claim 3 further comprising the step of utilizing the queue identification data sent to the microprocessor to determine which of the different interrupt handling routines are selected for linking.
Claim 6
Dependent Claim
140 words
In a computing system having a master sub-system and at least one slave sub-system in which a plurality of events are monitored, a method for organizing and handling recurring microprocessor interrupts comprising the steps of: organizing events into respective groups which have common interrupt handling requirements, each respective group having a different set of interrupt handling requirements; providing a different interrupt handling routine for each group; providing a data storage queue for each group; storing at least one data word for each event requiring interrupt attention in its respective queue; sequentially linking together different interrupt handling routines into a linked interrupt handling routine; and initiating the linked interrupt handling routine whereby each data word in each queue associated with the linked interrupt handling routine is serviced by a microprocessor in the master sub-system before exiting the linked interrupt handling routine.
Claim 7
Dependent Claim
140 words
In a computing system having a master sub-system and at least one slave sub-system in which a plurality of events are monitored, a method for organizing and handling recurring microprocessor interrupts comprising the steps of: organizing events into respective groups which have common interrupt handling requirements, each respective group having a different set of interrupt handling requirements; providing a different interrupt handling routine for each group; providing a data storage queue for each group; storing at least one data word for each event requiring interrupt attention in its respective queue; sequentially linking together different interrupt handling routines into a linked interrupt handling routine; and initiating the linked interrupt handling routine whereby each data word in each queue associated with the linked interrupt handling routine is serviced by a microprocessor in the master sub-system before exiting the linked interrupt handling routine.
Claim 8
Dependent Claim
35 words
The method according to claim 5 wherein said step of linking of the different interrupt handling routines further comprises the step of determining if any event data is stored in the queues to be serviced.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-27 | 1997-12-27 | 1998-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-27 | 2001-12-27 | 2002-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-27 | 2005-12-27 | 2006-06-28 | $7700.00 | Window Closed / Lapsed |