Patent US4417913A successfully refreshed from Google Patents.
Patent US5698458A successfully refreshed from Google Patents.
US5698458A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiple well device and process of manufacture
Assignee: United Microelectronics Corp
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Filing: 1996-07-15
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Granted: 1997-12-16
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Expires: 2016-07-15
Abstract
Abstract A method of manufacture of a semiconductor device comprises forming a silicon dioxide film upon the surface of said device, forming patterns of silicon nitride upon the surface of said silicon dioxide film, ion implanting ions into said substrate adjacent to at least some of said silicon nitride patterns for well regions of a first polarity, forming a mask over said device, and deeply ion implanting with ions of opposite polarity into well regions of opposite polarity.
Inventors
- 👤 Chen-Chiu Hsue
- 👤 Sun-Chieh Chien
- 👤 Chung-Yuan Lee
- 👤 Ming-Tzong Yang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:04
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
253 words
A method of fabricating a semiconductor device on a substrate, the method comprising: forming a silicon oxide layer on said substrate with said silicon oxide layer having a top surface; ion implanting a first kind of N-type impurities through said silicon oxide layer into said substrate for N-well regions; forming and patterning a silicon nitride layer on said top surface of said silicon oxide layer with openings therethrough leaving exposed portions of said top surface; ion implanting N-type impurities of a second, heavier kind through said openings through said silicon nitride layer and through exposed portions of said top surface of said silicon oxide layer for doping the well regions to form field implant regions adjacent to said silicon nitride layer; forming a patterned mask over portions of said patterned silicon nitride layer and over portions of said top surface of said silicon oxide layer, said patterned mask having an opening leaving portions of said top surface and said patterned silicon nitride layer exposed which are to be a P-well; ion implanting P-type impurities through said openings in said patterned mask and exposed portions of said patterned silicon nitride layer and said silicon oxide layer for first P-well regions; performing a field oxidation process on portions of said substrate unprotected by said silicon nitride layer so that field oxide regions are formed overlying said field implant regions; stripping said silicon nitride layer; and forming a P-well mask over an N-well region and ion implanting P-type impurities forming second P-well regions in said substrate.
Claim 2
Independent Claim
253 words
A method of fabricating a semiconductor device on a substrate, the method comprising: forming a silicon oxide layer on said substrate with said silicon oxide layer having a top surface; ion implanting a first kind of N-type impurities through said silicon oxide layer into said substrate for N-well regions; forming and patterning a silicon nitride layer on said top surface of said silicon oxide layer with openings therethrough leaving exposed portions of said top surface; ion implanting N-type impurities of a second, heavier kind through said openings through said silicon nitride layer and through exposed portions of said top surface of said silicon oxide layer for doping the well regions to form field implant regions adjacent to said silicon nitride layer; forming a patterned mask over portions of said patterned silicon nitride layer and over portions of said top surface of said silicon oxide layer, said patterned mask having an opening leaving portions of said top surface and said patterned silicon nitride layer exposed which are to be a P-well; ion implanting P-type impurities through said openings in said patterned mask and exposed portions of said patterned silicon nitride layer and said silicon oxide layer for first P-well regions; performing a field oxidation process on portions of said substrate unprotected by said silicon nitride layer so that field oxide regions are formed overlying said field implant regions; stripping said silicon nitride layer; and forming a P-well mask over an N-well region and ion implanting P-type impurities forming second P-well regions in said substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-15 | 2001-06-16 | 2001-12-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-15 | 2005-06-16 | 2005-12-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-15 | 2009-06-16 | 2009-12-16 | $7700.00 | Window Closed / Lapsed |