Process for fabricating a lateral bipolar junction transistor

Claim 1

A process for fabricating a lateral bipolar junction transistor semiconductor device comprising the steps of: (1) on a predetermined position of a semiconductor substrate having a first conductivity type, forming a well region of a second conductivity type as a collector region of said transistor device; (2) forming a lightly-doped region of the first type in said substrate surrounded by said well region as a base region for said transistor; (3) forming on said substrate: (i) a first field oxide surrounded by said well region, and (ii) a second field oxide at an outer edge of said well region; (4) removing said first field oxide to form a recessed groove in a region being occupied by said first field oxide; (5) forming an alignment at an edge of said recessed groove; (6) forming sidewall spacers for said alignment; (7) utilizing said alignment and said sidewall spacers as masking for implanting impurities of the first conductivity type into said lightly-doped region, said impurities being thermally driven into a depth of said substrate to form a heavily-doped region of the first conductivity type in a deeper portion of said lightly-doped region; (8) utilizing said second field oxide as masking for implanting impurities of the first conductivity type into said substrate to form at least one contact area for said substrate; (9) utilizing said alignment and said sidewall spacers as masking for implanting impurities of the second conductivity type into said lightly-doped region to form an emitter region for said transistor; and (10) utilizing said second field oxide, said alignment and said sidewall spacers as masking for implanting impurities of the second conductivity type into said well region to form at least one contact area for said well region.