Patent US5689713A successfully refreshed from Google Patents.
US5689713A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for interrupt communication in a packet-switched computer system
Assignee: Sun Microsystems Inc
•
Filing: 1995-04-20
•
Granted: 1997-11-18
•
Expires: 2015-04-20
Abstract
Abstract An apparatus and method for handling interrupt requests from any of a plurality of interrupters to any of a plurality of interrupt handlers. Each interrupt handler includes an interrupt input request queue for holding a plurality of incoming interrupt requests. A system controller is connected to the interrupters and the interrupt handlers, and includes an input queue coupled to each interrupter for receiving a plurality of interrupt requests. The system controller includes a processor and a memory storing instructions for controlling its operation. The system controller also includes an output queue coupled to each interrupt handler (which in many cases will also be interrupters), and a counter for monitoring the current number, at any given time, of interrupt requests pending in each of the interrupt input queues in the interrupt handlers. When an interrupt request is sent from an interrupter, the system controller determines a target for the request, which may be by a target ID in the request or may be based upon a predetermined method to ensure even distribution of interrupt requests among all or a subset of the interrupt handlers. The system controller determines whether the target interrupt handler's input queue is full, and if not then it passes on the interrupt request and sends a positive acknowledgment to the interrupter. If the queue is full, then a negative acknowledgment is sent, and the interrupter then waits a random period of time and sends the interrupt request again. The target interrupt handler may thus accept multiple interrupt requests and process them in order without negative acknowledgments.
Inventors
- 👤 Kevin B. Normoyle
- 👤 Zahir Ebrahim
- 👤 Satyanarayana Nishtala
- 👤 William C. Van Loo
- 👤 Sun-Den Chen
- 👤 Charles E. Narad
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:19
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/54; G06F9/546; G06F13/00; G06F13/14; G06F13/20; G06F13/24
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
218 words
A method for handling interrupt requests from a first device to at least one of a second device and a third device via a system controller coupled to each of at least the first, second and third devices, said second and third devices being interruptible devices, each said device and the system controller including a processor and a memory storing instructions for execution by the respective processors, the second device being coupled to a first interrupt input queue and the third device being coupled to a second interrupt input queue, each said interrupt queue configured for accepting at least one interrupt request, the system controller being configured to store queue size information relating to respective sizes of said first and second input queues, the method including the steps of: (1) generating in the first device a first interrupt request with said second device as a destination device for said first interrupt request; (2) receiving said first interrupt request at the system controller; (3) based at least in part on said queue size information, determining in the system controller whether the first interrupt input queue is full, and if not, then: (3A) passing said first interrupt request to the second device; but if so, then: (3B) sending the first device a signal indicating non-acknowledgment of said first interrupt request.
Claim 2
Independent Claim
218 words
A method for handling interrupt requests from a first device to at least one of a second device and a third device via a system controller coupled to each of at least the first, second and third devices, said second and third devices being interruptible devices, each said device and the system controller including a processor and a memory storing instructions for execution by the respective processors, the second device being coupled to a first interrupt input queue and the third device being coupled to a second interrupt input queue, each said interrupt queue configured for accepting at least one interrupt request, the system controller being configured to store queue size information relating to respective sizes of said first and second input queues, the method including the steps of: (1) generating in the first device a first interrupt request with said second device as a destination device for said first interrupt request; (2) receiving said first interrupt request at the system controller; (3) based at least in part on said queue size information, determining in the system controller whether the first interrupt input queue is full, and if not, then: (3A) passing said first interrupt request to the second device; but if so, then: (3B) sending the first device a signal indicating non-acknowledgment of said first interrupt request.
Claim 3
Dependent Claim
26 words
The method of claim 1, further including, after step 3B, the step of resending said first interrupt request by the first device after a wait interval.
Claim 4
Dependent Claim
14 words
The method of claim 2, wherein the wait interval is a random time interval.
Claim 5
Dependent Claim
34 words
The method of claim 1 wherein said first interrupt request includes a target ID, including the step of the system controller determining the destination device of said first interrupt request from the target ID.
Claim 6
Dependent Claim
28 words
The method of claim 1, including the step of transmitting a data packet to the second device including information relating to the processing of said first interrupt request.
Claim 7
Dependent Claim
21 words
The method of claim 5, wherein the data packet includes an interrupt vector indicating an address for an interrupt service routine.
Claim 8
Dependent Claim
21 words
The method of claim 5, wherein the data packet includes at least one instruction to be executed by the second device.
Claim 9
Dependent Claim
19 words
The method of claim 5, wherein the data packet includes a relative priority level for said first interrupt request.
Claim 10
Dependent Claim
21 words
The method of claim 1, wherein said first interrupt input queue is configured for receiving a plurality of said interrupt requests.
Claim 11
Dependent Claim
25 words
The method of claim 1, wherein the second device is configured for continuing processing of ongoing operations while receiving at least one said interrupt request.
Claim 12
Dependent Claim
40 words
The method of claim 1, including, after step 3A, the steps of: determining in the second device whether it is an appropriate recipient for the interrupt request, and if so, then sending a positive interrupt acknowledgment to the system controller.
Claim 13
Independent Claim
190 words
An apparatus for handling interrupt requests from first device to at least one of a second device and a third device, said second and third devices being interruptible devices, each said device including a processor and a memory storing instructions for execution by the respective processors, including: a first interrupt input queue coupled to the second device for receiving at least one interrupt request; a second interrupt input queue coupled to the third device for receiving at least one interrupt request; a system controller coupled to at least the first, second and third devices and configured to store queue size information relating to respective sizes of said first and second interrupt input queues, and including a third input queue for receiving at least one interrupt request from said first device, a counter for monitoring a number of interrupt requests present in the first input queue, and logic configured to pass said interrupt request which is directed to said second device only if said first input queue is not full, the determination of whether said first input queue is full being based at least in part on said queue size information.
Claim 14
Independent Claim
190 words
An apparatus for handling interrupt requests from first device to at least one of a second device and a third device, said second and third devices being interruptible devices, each said device including a processor and a memory storing instructions for execution by the respective processors, including: a first interrupt input queue coupled to the second device for receiving at least one interrupt request; a second interrupt input queue coupled to the third device for receiving at least one interrupt request; a system controller coupled to at least the first, second and third devices and configured to store queue size information relating to respective sizes of said first and second interrupt input queues, and including a third input queue for receiving at least one interrupt request from said first device, a counter for monitoring a number of interrupt requests present in the first input queue, and logic configured to pass said interrupt request which is directed to said second device only if said first input queue is not full, the determination of whether said first input queue is full being based at least in part on said queue size information.
Claim 15
Dependent Claim
59 words
The apparatus of claim 12, wherein the system controller is configured for sending a positive acknowledgment to said first device if a given said interrupt request directed to said second device is passed to said second device and for sending a negative acknowledgment to said first device if said given interrupt request is not passed to said second device.
Claim 16
Dependent Claim
29 words
The apparatus of claim 13, wherein the first device is configured to resend a said interrupt request after a wait interval receiving a negative acknowledgement from said system controller.
Claim 17
Dependent Claim
15 words
The apparatus of claim 14, wherein said wait interval is a random interval of time.
Claim 18
Dependent Claim
20 words
The apparatus of claim 12, wherein said first input queue is configured for storing a plurality of said interrupt requests.
Claim 19
Dependent Claim
29 words
The apparatus of claim 12, wherein said first device further includes a data input queue for receiving at least one data packet correlated with a given said interrupt request.
Claim 20
Dependent Claim
20 words
The apparatus of claim 12, wherein the system controller is configured for determining a target device of said interrupt requests.
Claim 21
Dependent Claim
62 words
The apparatus of claim 18, wherein: a plurality of potential interrupt handlers are coupled to said system controller; said system controller is configured for tracking a history of said interrupt requests sent to each of said plurality of interrupt handlers; and said system controller is configured for selecting a target interrupt handier to receive an incoming interrupt request based upon said history.
Claim 22
Dependent Claim
36 words
The apparatus of claim 12, wherein said second device is configured for determining whether it is an appropriate target for a received interrupt request, and if so for sending a positive acknowledgment to said system controller.
References Cited (Backward Citations)
US4177515A
Cited
US4215399A
Cited
US4228503A
Cited
US4604500A
Cited
US4987535A
Cited
US4734882A
Cited
US4953072A
Cited
EP0317481A2
Cited
EP0380842A2
Cited
US5036459A
Cited
US5325536A
Cited
EP0468831A2
Cited
WO1992005458A1
Cited
US5428799A
Cited
EP0507571A2
Cited
US5542076A
Cited
EP0537899A1
Cited
US5481726A
Cited
US5319753A
Cited
EP0598535A1
Cited
US5557744A
Cited
EP0644489A2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-11-17 | 2001-05-19 | 2001-11-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-17 | 2005-05-19 | 2005-11-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-17 | 2009-05-19 | 2009-11-18 | $7700.00 | Window Closed / Lapsed |