Method and apparatus for signalling interrupt information in a data processing system

Abstract

Abstract An interrupt packet protocol for both interrupt requests and interrupt resets. Address bus packets are used to signal and transfer information. When an interrupt source has an interrupt request, it requests use of the address bus. When granted the bus, the interrupt source sends out an interrupt request packet. The interrupt controller processes the information and signals an interrupt to the processor. In a multiprocessing system, the interrupt controller may route the interrupt information to an appropriate processor. When the processor is done processing the interrupt, it will alert the interrupt controller to send a reset packet to the interrupt source. By sending interrupt information over the address bus, it allows for use of an underutilized resource, the address bus, and not use the busier data bus. The interrupt packets going over the address bus use the address lines already in the system at a cost of zero pins and zero wires. This is in contrast to prior methods, which used several interrupt lines. Since interrupts are transferred over the address bus, they are sequenced with other interrupts and with other system operations. This is helpful during debug because it makes interrupts more observable at a system level and less asynchronous to the system. Since interrupt information is defined in various fields in the interrupt packet instead of being hard-wired on the planar, this interrupt system is very programmable.

Inventors

• 👤 Ronad Xavier Arroyo
• 👤 William Brent Chandler
• 👤 George William Daly, Jr.

Bibliographic Details