EP0507571A2
Expired / Lapsed
EP
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Receiving buffer control system
Assignee: Fujitsu Ltd
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Filing: 1992-04-01
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Granted: —
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Expires: 2012-04-01
Abstract
Abstract A receiving buffer control system comprises a memory (4) having a buffer area (8) serving as a receiving buffer, data being applied to the memory via a bus, a write pointer (11) indicating a write address of the buffer area, and a read pointer (12) indicating a read address of the buffer area. An overrun/underrun detection circuit (17) detects a situation in which an overrun or an underrun will occur in the buffer area in response to the write address indicated by the write pointer and the read address indicated by the read pointer. A control part (9) disables the data from being written into and read out from the buffer area when the overrun/underrun detection circuit detects the situation.
Inventors
- 👤 Toshiyuki c/o Fujitsu Limited Shimizu
- 👤 Takeshi c/o Fujitsu Limited Horie
- 👤 Hiroaki c/o Fujitsu Limited Ishihata
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 05:46
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10; G06F5/12; G06F5/14; H; H04; H04L; H04L49/00; H04L49/90; H04L49/901; H04L49/9031; H04L49/9047; H04L49/9057
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
162 words
A receiving buffer control system comprising: a memory (4) having a buffer area serving as a receiving buffer (8), data being applied to said memory via a bus; write pointer means (11), coupled to said memory, for indicating a write address of the buffer area; and read pointer means (12), coupled to said memory, for indicating a read address of the buffer area, characterized in that said receiving buffer control system comprises overrun/underrun detection means (17), coupled to said write pointer means and said read pointer means, for detecting a situation in which an overrun or an underrun will occur in the buffer area in response to the write address indicated by said write pointer means and said read address indicated by said read pointer means; and control means (9), coupled to said memory and said overrun/underrun detection means, for disabling the data from being written into and read out from the buffer area when said overrun/underrun detection means detects said situation.
Claim 2
Dependent Claim
57 words
A receiving buffer control system as claimed in claim 1, characterized by further comprising updating means (12′) for holding an advanced read address which precedes, by a predetermined address value, to the read address indicated by said read pointer means and for updating the read address indicated by said read pointer means by said advanced read address.
Claim 3
Dependent Claim
50 words
A receiving buffer control system as claimed in claim 1, characterized by further comprising means (3) for writing an external read address into said read pointer means,said external read address indicating split data in the buffer area so that said split data are continuously read out from the buffer area.
Claim 4
Dependent Claim
36 words
A receiving buffer control system as claimed in claim 2, characterized by further comprising means (3) for determining, on the basis of the advanced read address, whether or not there is data in the buffer area.
Claim 5
Dependent Claim
102 words
A receiving buffer control system as claimed in claim 1, characterized in that: said receiving buffer control system further comprises register means (15, 16) for holding a first base address of a logical address type and a second base address of a real address type; each of said first and second base addresses is used for updating the write address indicated by the write pointer means and the read address indicated by the read pointer means; and either said first base address or said second base address is used on the basis of the type of data input to the buffer area.
Claim 6
Dependent Claim
53 words
A receiving buffer control system as claimed in claim 1, characterized in that: said memory comprises a plurality of buffer areas; and said receiving buffer control system comprises means for detecting the type of data and for selecting one of the plurality of buffer areas on the basis of the type of data.
Claim 7
Dependent Claim
96 words
A receiving buffer control system as claimed in claim 6, characterized in that: said write pointer means comprises a plurality of write pointers (WTP0, WTP1, WTP2) respectively provided for said buffer areas; said read pointer means comprises a plurality of read pointers (RDP0, RDP1, RDP2) respectively provided for said buffer areas; said overrun/underrun detection means detects, for each of said buffer areas, said situation; and said control means disables, for each of said buffer areas, the data from being written into and read out from the buffer area when said overrun/underrun detection means detects said situation.
Claim 8
Dependent Claim
38 words
A receiving buffer control system as claimed in claim 7, characterized by further comprising means (43, 44) for selecting one of the write pointers and one of the read pointers on the basis of the type of data.
Claim 9
Dependent Claim
56 words
A receiving buffer control system as claimed in claim 1, characterized by further comprising: a cache memory (34) into which data identical to the data written into said buffer area is written; and means (27-33), operatively coupled to said updating means, for invalidating the data in the cache memory when said advanced read address is output.
Claim 10
Dependent Claim
25 words
A receiving buffer control system as claimed in claim 2, characterized in that said updating means comprises a register (12′) storing the advanced read address.
References Cited (Backward Citations)
No citation records indexed.
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