US5428799A
Expired / Lapsed
US
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Redirection of interrupts to microprocessors
Assignee: Hewlett Packard Development Co LP
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Filing: 1994-05-27
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Granted: 1995-06-27
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Expires: 2014-05-27
Abstract
Abstract A redirector in either software or hardware can is used to distribute global interrupts among all processors of a multiprocessor (MP) system, which may have multiple architecturally-isolated buses. When redirecting interrupts using software, a default processor receives all interrupts and redirects them to destination processors. When redirecting interrupts using hardware, a discrete redirector in hardware forwards all interrupts to particular processors based on a routing, or look-up, table. Another implementation incorporates interrupt snooping with either software or hardware interrupt redirection where interrupt response is critical for I/O cards.
Inventors
- 👤 Greg Woods
- 👤 Carol Bassett
- 👤 Robert Campbell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 11:00
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
139 words
A system for increasing the performance of a multiprocessor computer system, comprising: a shared memory; two or more processors coupled to said shared memory by a system bus, each of said two or more processors configured to transmit global interrupts to another two or more processors via said system bus; a system interrupt controller, coupled to said system bus, configured to receive and retransmit all of said global interrupts transmitted by said two or more processors; and a redirector, coupled to said system bus, configured to communicate with said system interrupt controller and said two or more processors, said redirector configured to receive all of said global interrupts retransmitted by said system interrupt controller, said redirector further configured to transmit interrupt data associated with said retransmitted global interrupts directly to a destination processor of said two or more processors.
Claim 2
Independent Claim
139 words
A system for increasing the performance of a multiprocessor computer system, comprising: a shared memory; two or more processors coupled to said shared memory by a system bus, each of said two or more processors configured to transmit global interrupts to another two or more processors via said system bus; a system interrupt controller, coupled to said system bus, configured to receive and retransmit all of said global interrupts transmitted by said two or more processors; and a redirector, coupled to said system bus, configured to communicate with said system interrupt controller and said two or more processors, said redirector configured to receive all of said global interrupts retransmitted by said system interrupt controller, said redirector further configured to transmit interrupt data associated with said retransmitted global interrupts directly to a destination processor of said two or more processors.
Claim 3
Dependent Claim
39 words
The system of claim 1, wherein said redirector and said system interrupt controller comprise: one or more program interrupt controllers; and software operated upon by a default processor of said two or more processors of the multiprocessor computer system.
Claim 4
Dependent Claim
18 words
The system of claim 1, wherein one or more of said two or more processors is a microprocessor.
Claim 5
Dependent Claim
16 words
The system of claim 1, wherein said multiprocessor computer system is implemented in a personal computer.
Claim 6
Dependent Claim
18 words
The system of claim 1, wherein said system interrupt controller and said redirector are incorporated on an ASIC.
Claim 7
Dependent Claim
33 words
The system of claim 1, wherein said redirector comprises a vector translation sender corresponding to said system interrupt controller and a vector translation receiver corresponding to each of said two or more processors.
Claim 8
Dependent Claim
13 words
The system of claim 1, wherein said two or more processors are nonhomogeneous.
Claim 9
Dependent Claim
30 words
The system of claim 1, wherein one or more of said two or more processors is coupled to said system bus via buses which are architecturally isolated from each other.
Claim 10
Independent Claim
156 words
A method for increasing the performance of a multiprocessor computer system, the multiprocessor system having two or more processors, a system interrupt controller, and a redirector, the two or more processors, system interrupt controller, and redirector coupled to and communicating with each other via a system bus, the method comprising the steps of: (1) receiving, in the system interrupt controller, a global interrupt from one of the two or more processors; (2) determining, at the system interrupt controller, the priority of said global interrupt and an associated global interrupt vector; (3) transmitting said global interrupt vector from the system interrupt controller to the redirector; (4) determining, at the redirector, a system bus address of a destination processor of the two or more processors for receiving said global interrupt; (5) translating said global interrupt into a destination processor dependent vector; and (6) notifying said destination processor of said global interrupt by transmitting said destination processor dependent vector.
Claim 11
Independent Claim
156 words
A method for increasing the performance of a multiprocessor computer system, the multiprocessor system having two or more processors, a system interrupt controller, and a redirector, the two or more processors, system interrupt controller, and redirector coupled to and communicating with each other via a system bus, the method comprising the steps of: (1) receiving, in the system interrupt controller, a global interrupt from one of the two or more processors; (2) determining, at the system interrupt controller, the priority of said global interrupt and an associated global interrupt vector; (3) transmitting said global interrupt vector from the system interrupt controller to the redirector; (4) determining, at the redirector, a system bus address of a destination processor of the two or more processors for receiving said global interrupt; (5) translating said global interrupt into a destination processor dependent vector; and (6) notifying said destination processor of said global interrupt by transmitting said destination processor dependent vector.
Claim 12
Dependent Claim
32 words
The method of claim 9, wherein said step (4) comprises the step of: (a) searching a look-up table in a memory unit to determine said system bus address of said destination processor.
Claim 13
Independent Claim
139 words
A system for increasing the performance of a multiprocessor computer system, comprising: a shared memory; two or more processors coupled to said shared memory by a system bus, each of said two or more processors configured to transmit global interrupts via said system bus; interrupt controller means, coupled to said system bus, for controlling said global interrupts transmitted by said two or more processors, said interrupt controller means receiving and retransmitting all of said global interrupts; receiving means for receiving all of said retransmitted global interrupts from said interrupt controller means; address determination means, coupled to said receiving means, for determining an intended destination processor of said two or more processors to receive said global interrupts; and transmit means, coupled to said address determination means, for transmitting interrupt data associated with said global interrupts directly to said destination processor.
Claim 14
Independent Claim
139 words
A system for increasing the performance of a multiprocessor computer system, comprising: a shared memory; two or more processors coupled to said shared memory by a system bus, each of said two or more processors configured to transmit global interrupts via said system bus; interrupt controller means, coupled to said system bus, for controlling said global interrupts transmitted by said two or more processors, said interrupt controller means receiving and retransmitting all of said global interrupts; receiving means for receiving all of said retransmitted global interrupts from said interrupt controller means; address determination means, coupled to said receiving means, for determining an intended destination processor of said two or more processors to receive said global interrupts; and transmit means, coupled to said address determination means, for transmitting interrupt data associated with said global interrupts directly to said destination processor.
Claim 15
Dependent Claim
36 words
The system of claim 11, wherein one or more of said two or more processors is coupled to said system bus via a bus which is architecturally isolated from other buses in the multiprocessor computer system.
Claim 16
Dependent Claim
44 words
The system of claim 11, wherein said determination means comprises a look-up table in a random access memory, said lookup table containing: an address of said destination processor; an interrupt vector associated with said global interrupt; and a priority level of said global interrupt.
Claim 17
Independent Claim
262 words
A system for increasing the performance of a multiprocessor computer system, comprising: a shared memory; two or more processors coupled to said shared memory by a system bus, each of said two or more processors configured to transmit global interrupts to another two or more processors via said system bus; a system interrupt controller, coupled to said system bus, configured to receive and retransmit all of said global interrupts transmitted by said two or more processors, said system interrupt controller including, one or more first programmable interrupt controllers coupled to said system bus, a first discrete logic, coupled to said one or more first programmable interrupt controllers, implemented by a first plurality of programmable logic arrays, configured to control said system interrupt controller, and a first memory unit, coupled to said discrete logic, configured to store said interrupt data; and a redirector, coupled to said system bus, configured to communicate with said system interrupt controller and said two or more processors, said redirector configured to receive all of said global interrupts retransmitted by said system interrupt controller, said redirector further configured to transmit interrupt data associated with said retransmitted global interrupts directly to a destination processor of said two or more processors, said redirector including, one or more second programmable interrupt controllers coupled to said system bus, a second discrete logic, coupled to said one or more second programmable interrupt controllers, implemented by a second plurality of programmable logic arrays, configured to control said redirector, and a second memory unit, coupled to said second discrete logic, configured to store said interrupt data.
Claim 18
Independent Claim
262 words
A system for increasing the performance of a multiprocessor computer system, comprising: a shared memory; two or more processors coupled to said shared memory by a system bus, each of said two or more processors configured to transmit global interrupts to another two or more processors via said system bus; a system interrupt controller, coupled to said system bus, configured to receive and retransmit all of said global interrupts transmitted by said two or more processors, said system interrupt controller including, one or more first programmable interrupt controllers coupled to said system bus, a first discrete logic, coupled to said one or more first programmable interrupt controllers, implemented by a first plurality of programmable logic arrays, configured to control said system interrupt controller, and a first memory unit, coupled to said discrete logic, configured to store said interrupt data; and a redirector, coupled to said system bus, configured to communicate with said system interrupt controller and said two or more processors, said redirector configured to receive all of said global interrupts retransmitted by said system interrupt controller, said redirector further configured to transmit interrupt data associated with said retransmitted global interrupts directly to a destination processor of said two or more processors, said redirector including, one or more second programmable interrupt controllers coupled to said system bus, a second discrete logic, coupled to said one or more second programmable interrupt controllers, implemented by a second plurality of programmable logic arrays, configured to control said redirector, and a second memory unit, coupled to said second discrete logic, configured to store said interrupt data.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-26 | 1998-12-26 | 1999-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-26 | 2002-12-26 | 2003-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-26 | 2006-12-26 | 2007-06-27 | $7700.00 | Window Closed / Lapsed |