US4918599A
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US
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Interrupt control system
Assignee: Fujitsu Ltd
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Filing: 1986-09-29
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Granted: 1990-04-17
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Expires: 2006-09-29
Abstract
Abstract An interrupt control system in which a main process device executes an interrupt process, having a high process priority. The process priority is registered in a table, corresponding to each interrupt generating source, and an intermediate process device receives an interrupt signal from each interrupt generating source, obtains the corresponding process priority from the table and informs the main process device of the interruption. Accordingly, the process priority can be easily changed, and the system has a small size because the interrupt circuit for the main process device is centralized.
Inventors
- 👤 Shigeru Hashimoto
- 👤 Yasuyuki Higashiura
- 👤 Yoshiyasu Sugimura
- 👤 Hisayuki Nishimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:37
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F9/4818; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
205 words
An interrupt control system in a process execution system having a plurality of sources for generating an interrupt signal, and a main process device for receiving said interrupt signal and interrupting a process being executed in accordance with a process priority of said sources generating said interrupt signal so as to execute the process for said interrupt signal, comprising: adapter means including (a) an intermediate process means for receiving an interrupt signal from the plurality of said interrupt signal generating sources connected thereto having different process priorities, and for receiving process priority information corresponding to the respective process priorities of the plurality of interrupt generating sources; (b) rewritable table memory means connected to said intermediate process means for providing the process priority information corresponding to said interrupt signal, and for storing the process priority information; (c) means for changing the process priority information for each of the sources for generating an interrupt signal in said rewritable table memory means, said intermediate process means includes means for receiving said interrupt signal, for obtaining from said rewritable table memory means the process priority information of the corresponding interrupt signal generating source, and for informing said main process device of the process priority together with said interrupt signal.
Claim 2
Dependent Claim
205 words
An interrupt control system in a process execution system having a plurality of sources for generating an interrupt signal, and a main process device for receiving said interrupt signal and interrupting a process being executed in accordance with a process priority of said sources generating said interrupt signal so as to execute the process for said interrupt signal, comprising: adapter means including (a) an intermediate process means for receiving an interrupt signal from the plurality of said interrupt signal generating sources connected thereto having different process priorities, and for receiving process priority information corresponding to the respective process priorities of the plurality of interrupt generating sources; (b) rewritable table memory means connected to said intermediate process means for providing the process priority information corresponding to said interrupt signal, and for storing the process priority information; (c) means for changing the process priority information for each of the sources for generating an interrupt signal in said rewritable table memory means, said intermediate process means includes means for receiving said interrupt signal, for obtaining from said rewritable table memory means the process priority information of the corresponding interrupt signal generating source, and for informing said main process device of the process priority together with said interrupt signal.
Claim 3
Dependent Claim
66 words
An interrupt control system according to claim 1, wherein said plurality of interrupt signal generating sources connected to said intermediate process means includes a plurality of file memory devices and a key input device, said key input device being set for said intermediate process means, so that the process priority of said intermediate process means is higher than that of said plurality of file memory devices.
Claim 4
Dependent Claim
69 words
An interrupt control system according to claim 1, wherein said main process device informs said intermediate process means of the process priority of each of said plurality of interrupt signal generating sources, wherein said rewritable table memory means is formed by a rewritable memory, and wherein said intermediate process means stores the process priority in said rewritable memory corresponding to each of said plurality of interrupt signal generating sources.
Claim 5
Dependent Claim
68 words
An interrupt control system according to claim 1, wherein said main process device includes a plurality of interrupt signal receiving terminals, each corresponding to one of said process priorities, and wherein said intermediate process means, in accordance with said process priority obtained from said rewritable table memory means, selectively starts a signal line corresponding to a plurality of interrupt signal lines connected to said interrupt signal receiving terminals.
Claim 6
Dependent Claim
72 words
An interrupt control system according to claim 4, wherein said main process device and said adapter means are connected by a bus signal line, wherein the interrupt signal generating sources, which are connected to said adapter means, are not connected to said bus signal line, and wherein the interrupt signal which is generated by said interrupt signal generating sources not connected to said adapter means is supplied to said interrupt signal line.
Claim 7
Dependent Claim
36 words
An interrupt control system according to claim 4, wherein said table means stores the process priority as code, and wherein said intermediate process means converts said code so as to start one selected interrupt signal line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-16 | 1993-10-16 | 1994-04-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-16 | 1997-10-16 | 1998-04-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-16 | 2001-10-16 | 2002-04-17 | $7700.00 | Window Closed / Lapsed |