EP0598535A1
Expired / Lapsed
EP
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Pending write-back controller for a cache controller coupled to a packet switched memory bus
Assignee: Xerox Corp
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Filing: 1993-11-08
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Granted: —
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Expires: 2013-11-08
Abstract
Abstract A write-back cache control system having a pending write-back cache controller in a multiprocessor cache memory structure. The processor subsystems in the multiprocessor system are coupled together using a high-speed synchronous packet switching bus called a memory bus. Each processor subsystem has an associated cache control system. When a processor's cache control system does not have a required memory location in the cache memory, it broadcasts a memory request packet across the memory bus for the required data. If an owned cache line is being replaced, the cache control system copies the old cache line data to the pending write-back cache controller which is responsible for the write-backs of owned cache lines to main memory. The cache control system then transfers ownership of the old replaced cache line to the pending write-back controller. When the cache control system receives the new cache line information from the memory bus, it immediately replaces the cache line and allows the processing to continue. By buffering the old cache line in the pending write-back controller, the cache control system allows the new cache line to be requested before the old cache line is written back to main memory thereby reducing the cache line replacement latency period.
Inventors
- 👤 Bjorn Liencres
- 👤 Douglas Lee
- 👤 Pradeep S. Sindhu
- 👤 Tung Pham
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 06:21
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0804; G06F12/0806; G06F12/0815; G06F12/0831
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
182 words
In a computer system induding at least one processor subsystem and a main memory, said processor subsystem and main memory coupled via a packet-switched memory bus, a write-back cache memory system in each of said processor subsystems, said write-back cache memory system comprising: a cache memory, said cache memory comprising at least one cache line, each of said cache lines storing information; a cache directory, said cache directory storing an address tag and a plurality of status bits for each cache line in said cache memory, said plurality of status bits including a valid bit and an owned bit; a cache control system, said cache control system coupled to said cache memory and said cache directory, said cache control system further coupled to said packet switched memory bus, said cache control system maintaining said cache directory; and a pending write-back controller, said pending write-back controller coupled to said cache control system, said pending write-back controller buffering a plurality of owned cache lines which have been replaced, said pending write-back controller responsible for writing back the owned cache lines to said main memory.
Claim 2
Dependent Claim
184 words
The write-back cache memory system as claimed in claim 1 wherein said pending write-back controller further comprises: a data memory for storing said plurality of owned cache lines, each of said owned cache lines having a corresponding main memory address; an address tag and a plurality of status bits for each of said plurality of owned cache lines stored in the data memory, said address tag being the corresponding main memory address of said owned cache line; a write-back memory, said write-back memory storing an encoded set of owned cache lines stored in said data memory which must be written back to said main memory; a read request memory, said read request memory storing a set of read requests received over said packet-switched memory bus, said read requests requesting the owned cache lines in said data memory; and a pending write-back control logic unit for controlling said pending write-back controller such that a read reply is sent for each read request stored in said read request memory and each owned cache line listed in said write-back memory is written back to said main memory.
Claim 3
Dependent Claim
29 words
The write-back cache memory system as claimed in claim 2 wherein said plurality of status bits in said pending write-back controller comprise a valid bit and an owned bit.
Claim 4
Dependent Claim
69 words
The write-back cache memory system as claimed in claim 3 wherein said pending write-back control logic unit further comprises means for resetting the owned status bit for an owned cache line stored in said data memory when a write transaction occurs on said memory bus to the corresponding main memory address of the modified cache line such that said pending write-back controller does not write-back said owned cache line.
Claim 5
Dependent Claim
25 words
The write-back cache memory system as claimed in claim 4 wherein said write-back memory in said pending write-back control logic comprises a first-in-first-out (FIFO) memory.
Claim 6
Dependent Claim
26 words
The write-back cache memory system as claimed in claim 5 wherein said read request memory in said pending write-back control logic comprises a first-in-first-out (FIFO) memory.
Claim 7
Dependent Claim
97 words
The write-back cache memory system as claimed in claim 6 wherein said cache control system is divided into two separate cache controllers, said cache control system comprising: a bus cache controller, said bus cache controller interfacing said cache control system to the packet-switched memory bus, said bus cache controller having a first cache directory; a processor cache controller, said processor cache controller interfacing said cache memory to a processor, said processor cache controller having a second cache directory; and a packet-switched cache bus, said packet-switched cache bus coupling said bus cache controller and said processor cache controller.
Claim 8
Dependent Claim
37 words
The write-back cache memory system as claimed in claim 7 wherein each of said cache lines are further subdivided into M subblocks, each of said subblocks having separate status bits, each of said subblocks being treated separately.
Claim 9
Dependent Claim
218 words
In a computer system including at least one processor subsystem and a main memory, said processor subsystem and main memory coupled via a packet-switched memory bus, a write-back cache memory system in each of said processor subsystems, said write-back cache memory system comprising: a cache memory, said cache memory comprising at least one cache line, each of said cache lines storing lines of information, each of said lines of information having a corresponding main memory address; a cache directory, said cache directory storing an address tag and a set of status bits for each cache line in said cache memory, said address tag being the corresponding main memory address for said cache line; a write-back cache control system, said write-back cache control system maintaining said cache memory and said cache directory; means for requesting a new line of information for a cache line storing an owned line in said cache memory over said memory bus; means for copying the owned line of information from the cache line in the cache memory to a pending write-back controller; means for replacing said owned line of information with said requested new line of information in the cache line of the cache memory; and means for writing back said owned line of information in the pending write-back controller to said main memory.
Claim 10
Dependent Claim
127 words
The write-back cache memory system as claimed in claim 9 wherein said pending write-back controller further comprises: means for storing said owned line of information copied from said cache memory; means for storing an address tag and a plurality of status bits for said owned line of information, said address tag being the corresponding main memory address of said owned line of information; means for receiving and storing a plurality of read requests, said read requests requesting the owned line of information; means for replying to said plurality of read requests with a read request reply containing said owned line of information; and means for writing back said old line of information to main memory when no read requests for said owned line of information are pending.
Claim 11
Dependent Claim
29 words
The write-back cache memory system as claimed in claim 10 wherein said plurality of status bits in said pending write-back controller comprise a valid bit and an owned bit.
Claim 12
Dependent Claim
67 words
The write-back cache memory system as claimed in claim 11 wherein said pending write-back controller further comprises: means for receiving a plurality of write requests, said write requests writing to the main memory address of the owned line of information; means for responding to said write requests by resetting the owned bit the line of information such that said line is not written back to main memory.
Claim 13
Dependent Claim
29 words
The write-back cache memory system as claimed in claim 12 wherein each of said cache lines are further subdivided into M subblocks, each of said subblocks being treated separately.
Claim 14
Dependent Claim
157 words
In a computer system having at least one processor subsystem and a main memory coupled via a packet switched memory bus, each of said processor subsystems having a write-back cache memory system comprising a cache memory having at least one cache line, a method of replacing the cache lines in the processor subsystem cache memories, said method comprising the steps of: requesting a new line of information for a cache line in said processor subsystem cache memory over said memory bus; transferring an owned line of information from the cache line of said processor subsystem cache memory to a pending write-back controller; receiving said requested new line of information into the cache line of said processor subsystem cache memory ; writing back said owned line of information in the pending write-back controller to the main memory, said step of writing back said owned line of information occurring after said step of requesting a new line of information.
Claim 15
Dependent Claim
69 words
The method of replacing the cache lines in the processor subsystem cache memories as claimed in claim 14 wherein said step of writing back said owned line of information in the pending write-back controller further comprises: receiving read requests for the owned line of information; and responding to said read requests for the owned line of information by sending a read request reply containing the owned line of information.
Claim 16
Dependent Claim
70 words
The method of replacing the cache lines in the processor subsystem cache memories as claimed in claim 15 wherein said step of writing back said owned line of information in the pending write-back controller further comprises: receiving write requests to the owned line of information; and responding to said write requests to the owned line of information by not writing back said owned line of information to the main memory.
Claim 17
Dependent Claim
37 words
The method of replacing the cache lines in the processor subsystem cache memories as claimed in claim 11 wherein each of said cache lines are further subdivided into M subblocks, each of said subblocks being treated separately.
References Cited (Backward Citations)
WO1990005953A1
Cited
EP0468831A2
Cited
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