US5557744A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiprocessor system including a transfer queue and an interrupt processing unit for controlling data transfer between a plurality of processors
Assignee: Fujitsu Ltd
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Filing: 1993-07-28
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Granted: 1996-09-17
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Expires: 2013-07-28
Abstract
Abstract A multiprocessor system having a plurality of processors connected in parallel with each other through a network for performing mutual communication. Each processor includes a transfer queue unit for storing transfer requests, a main storage, a reception unit for receiving a transfer request from another processor, and a transmission unit for sending designated data to another processor when the transfer request is enqueued in the transfer queue unit. Each processor also includes a first register for storing information indicating whether the transfer queue unit is full, i.e. has an area available for storing a transfer request, and a second register for indicating whether a transfer request is a valid transfer request during a reception operation. A save unit is connected to the reception unit for temporarily saving a transfer request, and an enqueuing unit is provided for enqueuing a transfer request from the save unit to the transfer queue unit. An interruption processing unit receives an interrupt request from the reception unit, supervises the vacant/full state of the transfer queue unit, i.e. monitors whether the transfer queue unit has an area available for storing a transfer request, and outputs an enqueuing request to the enqueuing unit to realize the interrupt request.
Inventors
- 👤 Kazushige Kobayakawa
- 👤 Shigeru Nagasawa
- 👤 Masayuki Ikeda
- 👤 Haruhiko Ueno
- 👤 Naoki Shinjo
- 👤 Teruo Utsumi
- 👤 Masami Dewa
- 👤 Kenichi Ishizaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:23
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/17; G06F13/00; G06F13/14; G06F13/20; G06F13/24
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
253 words
A multiprocessor system formed of a plurality of processors connected in parallel with each other through a network for performing communication, each processor comprises: transfer queue means for temporarily storing a plurality of transfer requests; a main storage for storing data to be enqueued; reception means queue means for receiving transfer requests issued by other processors in the multiprocessor system, and sequentially enqueuing the received transfer requests to the transfer queue means; transmission means connected to the transfer queue means for sending data designated by a transfer request from the main storage to another processor in the multiprocessor system when that transfer request is enqueued in the transfer queue means; a first register connected to the reception means for indicating whether the transfer queue means has an area available for storing a transfer request; a second register connected to the reception means for indicating whether a transfer request is a valid transfer request; save means connected to the reception means for temporarily saving a transfer request; enqueuing means connected between the save means and the transfer queue means for enqueuing a transfer request saved by the save means to the transfer queue means; and interruption processing means connected to the reception means and the first register for receiving an interrupt request from the reception means, monitoring whether the transfer queue means has an area available for storing a transfer request and outputting an enqueuing request to the enqueuing means when the transfer queue means has an area available for storing a transfer request.
Claim 2
Dependent Claim
253 words
A multiprocessor system formed of a plurality of processors connected in parallel with each other through a network for performing communication, each processor comprises: transfer queue means for temporarily storing a plurality of transfer requests; a main storage for storing data to be enqueued; reception means queue means for receiving transfer requests issued by other processors in the multiprocessor system, and sequentially enqueuing the received transfer requests to the transfer queue means; transmission means connected to the transfer queue means for sending data designated by a transfer request from the main storage to another processor in the multiprocessor system when that transfer request is enqueued in the transfer queue means; a first register connected to the reception means for indicating whether the transfer queue means has an area available for storing a transfer request; a second register connected to the reception means for indicating whether a transfer request is a valid transfer request; save means connected to the reception means for temporarily saving a transfer request; enqueuing means connected between the save means and the transfer queue means for enqueuing a transfer request saved by the save means to the transfer queue means; and interruption processing means connected to the reception means and the first register for receiving an interrupt request from the reception means, monitoring whether the transfer queue means has an area available for storing a transfer request and outputting an enqueuing request to the enqueuing means when the transfer queue means has an area available for storing a transfer request.
Claim 3
Dependent Claim
74 words
A multiprocessor system as claimed in claim 1, further comprising a write pointer connected between the transfer queue means and the transmission means and incremented by the reception means for indicating an available area to be written in the transfer queue means, and a read pointer connected between the transfer queue means and the transmission means and incremented by the transmission means for indicating an area to be read from the transfer queue means.
Claim 4
Dependent Claim
24 words
A multiprocessor system as claimed in claim 1, wherein the interruption processing means comprises one of an operating system and a data processing program.
Claim 5
Dependent Claim
52 words
A multiprocessor system as claimed in claim 1, wherein the interruption processing means sets the first register within the processor containing that transfer queue means to indicate that the transfer queue means does not have an area available for storing a transfer request regardless of the state of the transfer queue means.
Claim 6
Dependent Claim
52 words
A multiprocessor system as claimed in claim 1, wherein the interruption processing means sets the second register within the processor containing that transfer queue means to indicate that the transfer request is a valid request and the reception means ignores a transfer request when the second register indicates a non-valid transfer request.
Claim 7
Dependent Claim
26 words
A multiprocessor system as claimed in claim 1, wherein the transfer queue means enqueues a transfer request issued by the processor containing that transfer queue means.
Claim 8
Dependent Claim
177 words
A multiprocessor system as claimed in claim 1, wherein the reception means includes a rejection unit for ignoring a transfer request sent from another processor, a decision unit for determining whether the first register indicates the transfer queue means does not have an available area for storing a transfer request when receiving the transfer request sent from another processor, a detection unit for detecting whether the transfer queue means has an area available for storing a transfer request when the first register indicates a vacant state, a save unit for saving the transfer request sent from another processor into the save means when the decision unit determines the first register indicates the transfer queue means does not have an area available for storing a transfer request and when the detection unit detects the transfer queue means does not have an area available for storing a transfer request, and an issuing unit for issuing an interrupt request to the interruption processing means when the save unit saves the transfer request sent from another processor into the save means.
Claim 9
Dependent Claim
76 words
A multiprocessor system as claimed in claim 7, wherein, when the interruption processing means receives the interrupt request from the issuing unit, the interruption processing means detects whether the transfer queue means has an area available for storing a transfer request and, when an area is available for storing a transfer request issues an enqueuing request to the enqueuing means so as to enqueue the transfer request sent from another processor to the transfer queue means.
References Cited (Backward Citations)
US4032899A
Cited
WO1984003192A1
Cited
US4646294A
Cited
US5161215A
Cited
US4672570A
Cited
US5369749A
Cited
EP0405545A2
Cited
US5016221A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-17 | 2000-03-18 | 2000-09-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-17 | 2004-03-18 | 2004-09-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-17 | 2008-03-18 | 2008-09-17 | $7700.00 | Window Closed / Lapsed |