High-speed queue sequencer for a burst-switching communications system

Claim 1

A high-speed queue sequencer for use in a switch of a burst-switching communications system, a burst being a plurality of bytes, said system including a plurality of switches interconnected by time-division multiplexed communications links, each link having a plurality of frames within each second of time, each frame having a plurality of channels, each channel having communications capacity for the transmission of one byte, a byte being a predetermined number of bits, a bit being one binary digit, said system including a plurality of ports, each port being a component of a switch, said switch including a queue sequencer and at least one switching processor, said queue sequencer and switching processor(s) being coupled via a queue-sequencer bus, said queue sequencer comprising: (a) a data/address bus; (b) control means coupled with said data/address bus for controlling said queue sequencer, said control means including stored-program memory and execution means and queue-memory means for storing administrative information pertaining to bursts passing through said link switch; (c) enque/deque means coupled with said data/address bus, said enque means for performing the administration required for placing a burst on an output queue, said output queue being a list which indicates those bursts awaiting assignment to an output channel in a communications link, said deque means for assigning the highest priority burst on an output queue to an idle output channel of said communications link and removing said assigned burst from said output queue, said enque/deque means operating substantially in parallel with and independently of said control means; (d) request-holding means coupled with said data/address bus, for receiving requests from said switching processor(s), determining the priority of each request, storing said pending requests within priority classes, and outputting said requests within each priority class in the same time order as received, said request-holding means operating substantially in parallel with and independently of said control means; (e) input-interface means coupled between said queue-sequencer bus and said request-holding means, for providing an interface between said queue sequencer and said switching processor(s), said input-interface means having the ability to receive a request from a switching processor of said switch and to transmit said request to said request-holding means, said input-interface means operating substantially in parallel with and independently of said control means; and (f) output-interface means coupled between said data/address bus and said queue-sequencer bus, for providing an interface between said queue sequencer and said switching processor(s), said output interface means having the ability to transmit a buffer address to a switching processor, said output-interface means operating substantially in parallel with and independently of said control means; (g) whereby said queue sequencer operates substantially in parallel with and independently of said switching processor(s), and said queue sequencer acts on behalf of all switching processors of said switch.