EP0405545A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Data communication adapter and data communication terminal apparatus employing the same
Assignee: Hitachi Ltd
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Filing: 1990-06-28
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Granted: —
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Expires: 2010-06-28
Abstract
Abstract A data communication adapter (30) is connected between a signal transmission path (1) and a host processor unit (2) for producing frame data to be output to the signal transmission path. An internal host bus (62) is provided and used independent of the CPU dedicated bus (51). The transmission/reception data generated and interpreted by the host processor (41) is transferred via the internal host bus (62), a bus interface (61) and a system data bus (5) between a transmission memory (33) or a reception memory (17) and a buffer memory. The reception memory (host dedicated reception memory) (17) for storing only the reception data to be interpreted by the host processor (4) is separately provided with another reception memory (CPU dedicated reception memory) (56) for storing only the reception data to be interpreted by a CPU (52).
Inventors
- 👤 Shigeo Kuboki
- 👤 Norihiko Sugimoto
- 👤 Shunji Inada
- 👤 Kazuhisa Inada
- 👤 Tomoaki Aoki
- 👤 Masahiro Ueno
- 👤 Yasushi Nakamura
- 👤 Eiki Kondoh
- 👤 Toshihiko Tominaga
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 11:00
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/28; G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F13/128; G06F13/38; G06F13/382; G06F13/385
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
318 words
A data communication adapter apparatus (30) operatively connected between a signal transmission path (1) for transmitting both receive data and transmit data, and a host processor unit (2) for producing frame data to output the frame data therefrom, comprising: a central processing unit (CPU) (52) for producing the frame data and outputting the produced frame data; a transmission/reception control unit (59) operatively connected to said signal transmission path, for outputting the transmit data to said signal transmission path and for inputting the receive data from said signal transmission path; a bus interface (61) operatively connected to said host processing unit (2); an internal host bus (62) operatively connected to said bus interface (61); a CPU dedicated bus (51) operatively connected to said CPU (52); a FIFO (first-in-first-out) memory (33) whose input is operatively connected to said CPU dedicated bus and internal host bus, whose output is operatively connected to said transmission/reception control unit, and which stores therein the frame data derived from said CPU (52) and host processor (4), and also outputs said frame data to said transmission/reception control unit as said transmit data; a reception memory (MAC RAM 50) whose input is operatively connected to said transmission/reception control unit, whose output is operatively connected to said CPU dedicated bus, and which stores therein first frame data among the receive data inputted by said transmission/reception control unit, which is interpreted in said data communication adapter (30), and outputs said first frame data; a reception FIFO memory (17) whose input is operatively connected to said transmission/reception control unit (59), whose output is operatively connected to said internal host bus (62), and which stores therein second frame data among the receive data inputted by said transmission/reception control unit, which is interpreted by said host processor unit, and outputs said second frame data; and, a first memory (55) operatively connected between said bus interface (61) and said CPU dedicated bus (51).
Claim 2
Dependent Claim
318 words
A data communication adapter apparatus (30) operatively connected between a signal transmission path (1) for transmitting both receive data and transmit data, and a host processor unit (2) for producing frame data to output the frame data therefrom, comprising: a central processing unit (CPU) (52) for producing the frame data and outputting the produced frame data; a transmission/reception control unit (59) operatively connected to said signal transmission path, for outputting the transmit data to said signal transmission path and for inputting the receive data from said signal transmission path; a bus interface (61) operatively connected to said host processing unit (2); an internal host bus (62) operatively connected to said bus interface (61); a CPU dedicated bus (51) operatively connected to said CPU (52); a FIFO (first-in-first-out) memory (33) whose input is operatively connected to said CPU dedicated bus and internal host bus, whose output is operatively connected to said transmission/reception control unit, and which stores therein the frame data derived from said CPU (52) and host processor (4), and also outputs said frame data to said transmission/reception control unit as said transmit data; a reception memory (MAC RAM 50) whose input is operatively connected to said transmission/reception control unit, whose output is operatively connected to said CPU dedicated bus, and which stores therein first frame data among the receive data inputted by said transmission/reception control unit, which is interpreted in said data communication adapter (30), and outputs said first frame data; a reception FIFO memory (17) whose input is operatively connected to said transmission/reception control unit (59), whose output is operatively connected to said internal host bus (62), and which stores therein second frame data among the receive data inputted by said transmission/reception control unit, which is interpreted by said host processor unit, and outputs said second frame data; and, a first memory (55) operatively connected between said bus interface (61) and said CPU dedicated bus (51).
Claim 3
Dependent Claim
29 words
A data communication adapter apparatus (30) as claimed in Claim 1, wherein said first memory includes means accessible from said host processor unit to said data communication adapter (30).
Claim 4
Dependent Claim
30 words
A data communication adapter apparatus (30) as claimed in Claim 1, further comprising: a second memory (50) operatively connected between said bus interface (61) and the CPU dedicated bus (51).
Claim 5
Dependent Claim
32 words
A data communication adapter apparatus (30) as claimed in Claim 3, wherein said second memory (50) includes: means mutually accessible from both said host processor unit and said data communication adapter (30).
Claim 6
Dependent Claim
126 words
A data communication adapter apparatus (30) as claimed in Claim 1, wherein said transmission/reception control unit (59) includes means (77-2) for generating a parity bit so as to add said parity bit to the receive data; said bus interface (61) includes means (75-1) for performing a parity check with respect to said second frame data to which the parity bit is added, that has been read from said reception FIFO memory and inputted via said internal host bus; and, said data communication adapter (30) includes means (76- 1) for performing a parity check with respect to the first frame data to which the parity bit is added, that has been further read out from said reception memory (56) and inputted via said CPU dedicated bus (51).
Claim 7
Dependent Claim
127 words
A data communication adapter apparatus (30) as claimed in Claim 1, wherein said data communication adapter (30) further includes means (76-2) for producing a parity bit so as to add said parity bit to the frame data which has been generated by said CPU and inputted into said transmission FIFO memory (33); said bus interface includes means (75-1) for executing a parity check with respect to the frame data to which the parity bit derived from said host processor unit has been added, and for inputting said frame data via said internal host bus into said transmit FIFO memory; and, said transmission/reception control unit includes means (77-1) for performing a parity check with respect to the transmit data which has been read from the transmit FIFO memory.
Claim 8
Dependent Claim
108 words
A data communication adapter apparatus (30) as claimed in Claim 1, further comprising: means (120) for producing a first frame status based upon said first frame data among the receive data which have been received by said transmit/receive control unit, and also for producing a second frame status based upon said second frame data; means (65: 120-125) for storing said first frame status together with said first frame data into said receive memory (56); and, means (65: 121) for transferring said second frame status together with said second frame data via said receive FIFO memory, internal host bus (62) and bus interface (61) to said host processor unit.
Claim 9
Dependent Claim
60 words
A data communication terminal apparatus connected to a signal transmission path and including a data communication adapter (30) and a host processor unit (2) having a host processor for producing frame data and connected to the signal transmission path through the data communication adapter, characterized by a data communication adapter in accordance with one of the claims 1 to 7.
Claim 10
Dependent Claim
310 words
A data communication adapter apparatus (30) operatively connected between a signal transmission path for transmitting both receive data and transmit data, and a host processor unit for producing frame data to output the frame data therefrom, comprising: data processing means (52) for generating the frame data to output the frame data therefrom; transmission/reception means (59) operatively connected to said signal transmission path, for transmitting the transmit data to said signal transmission path and for inputting the receive data derived from said signal transmission path; first repeating means (61) for transmitting/receiving data between said host processor unit and said data communication adapter (30); first bus means (51) for performing a data transmission; second bus means (62) for performing the data transmission; second repeating means (55) capable of transmitting/receiving the data via said first repeating means (61) and data processing means (51) between said host processor unit and said data processing means (52); transmitting memory means (FIFO 33) for storing both the frame data which has been inputted from said host processor unit via said first repeating means and second bus means, and also the frame data which has been inputted from said data processing means (52) via said first bus means (51), and for outputting said both frame data to said transmission/reception means (59) as transmission data; first receiving memory means (MAC RAM 56) for storing therein first frame data to be interpreted by said data communication adapter apparatus among the receive data which have been inputted by said transmission/reception means (59), and for outputting said first frame data to said first bus means (51); and, second receiving memory means (FIFO 17) for storing therein second frame data to be interpreted by said host processor among the receive data which have been inputted by said transmission/reception means (59), and for outputting said second frame data to said second bus means (62).
Claim 11
Dependent Claim
310 words
A data communication adapter apparatus (30) operatively connected between a signal transmission path for transmitting both receive data and transmit data, and a host processor unit for producing frame data to output the frame data therefrom, comprising: data processing means (52) for generating the frame data to output the frame data therefrom; transmission/reception means (59) operatively connected to said signal transmission path, for transmitting the transmit data to said signal transmission path and for inputting the receive data derived from said signal transmission path; first repeating means (61) for transmitting/receiving data between said host processor unit and said data communication adapter (30); first bus means (51) for performing a data transmission; second bus means (62) for performing the data transmission; second repeating means (55) capable of transmitting/receiving the data via said first repeating means (61) and data processing means (51) between said host processor unit and said data processing means (52); transmitting memory means (FIFO 33) for storing both the frame data which has been inputted from said host processor unit via said first repeating means and second bus means, and also the frame data which has been inputted from said data processing means (52) via said first bus means (51), and for outputting said both frame data to said transmission/reception means (59) as transmission data; first receiving memory means (MAC RAM 56) for storing therein first frame data to be interpreted by said data communication adapter apparatus among the receive data which have been inputted by said transmission/reception means (59), and for outputting said first frame data to said first bus means (51); and, second receiving memory means (FIFO 17) for storing therein second frame data to be interpreted by said host processor among the receive data which have been inputted by said transmission/reception means (59), and for outputting said second frame data to said second bus means (62).
Claim 12
Dependent Claim
39 words
A data communication adapter apparatus (30) as claimed in Claim 9, wherein said second repeating means (55) includes means for being accessible from said host processor unit via said first repeating means (61) to said data communication adapter apparatus.
Claim 13
Dependent Claim
46 words
A data communication adapter apparatus (30) as claimed in Claim 9, further comprising: third repeating means (RAM 50) capable of transmitting/receiving the data between said host processor unit and said data communication adapter apparatus (30) via said first repeating means (62) and second bus means (51).
Claim 14
Dependent Claim
36 words
A data communication adapter apparatus (30) as claimed in Claim 11, wherein said third repeating memory (50) includes: means for being mutually accessible from both said host processor unit and said data communication adapter apparatus (30).
Claim 15
Dependent Claim
131 words
A data communication adapter apparatus (30) as claimed in Claim 9, wherein said transmission/reception means (59) includes means (77-2) for generating a parity bit so as to add said parity bit to the receive data; said first repeating means (61) includes means (75-1) for performing a parity check with respect to said second frame data to which the parity bit is added, that has been read from said second receiving memory means (17) and inputted via said second bus means (62); and, said data communication adapter apparatus (30) includes means (76-1) for performing a parity check with respect to the first frame data to which the parity bit is added, that has been further read out from said first receiving memory means (56) and inputted via said first bus means (51).
Claim 16
Dependent Claim
130 words
A data communication adapter apparatus (30) as claimed in Claim 9, wherein said data communication adapter apparatus (30) further includes means (76-2) for producing a parity bit so as to add said parity bit to the frame data which has been generated by said data processing means and inputted into said transmitting memory means (33); said first repeating means includes means (75-1) for executing a parity check with respect to the frame data to which the parity bit derived from said host processor unit has been added, and for inputting said frame data via said second bus means into said transmitting memory means; and, said transmission/reception means includes means (77-1) for performing a parity check with respect to the transmit data which has been read from the transmitting memory means.
Claim 17
Dependent Claim
109 words
A data communication adapter apparatus (30) as claimed in Claim 9, further comprising: means (120) for producing a first frame status based upon said first frame data among the receive data which have been received by said transmission/reception means, and also for producing a second frame status based upon said second frame data; means (65: 120-125) for storing said first frame status together with said first frame data into said first receiving memory (56); and, means (65:121) for transferring said second frame status together with said second frame data via said second receiving memory means, second bus means (62) and first repeating means (61) to said host processor unit.
Claim 18
Dependent Claim
59 words
A data communication terminal apparatus connected to a signal transmission path and including a data communication adapter (30) and a host processor unit (2) having host processor for producing frame data and connected to the signal transmission path through the data communication adapter, characterised by a data communication adapter in accordance with one of the claims 9 to 15.
References Cited (Backward Citations)
No citation records indexed.
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