First-in, first-out (FIFO) memory with variable commit point

Claim 2

An improvement in a FIFO memory that provides first-in, first-out digital data storage and retrieval, sequentially inputting and storing digital data and sequentially retrieving and outputting said stored digital data, said FIFO memory comprising addressable memory means having memory locations for addressably inputting, storing, retrieving and outputting said digital data, said FIFO memory further comprising W-pointer means for addressing one of said memory locations into which said digital data is to be stored, and R-pointer means for addressing one of said memory locations from which said stored digital data is to be retrieved, wherein said improvement comprises: C-pointer means for selectably addressing one of said memory locations which serves as a boundary between first and second subsets of said stored digital data within said FIFO memory; and commitment decision means for specifying said memory location to be addressed by said C-pointer means.

Claim 3

A FIFO memory means for providing first-in, first-out digital data storage and retrieval, sequentially inputting and storing digital data and sequentially retrieving and outputting said stored digital data, said digital data having start data and end data, said FIFO memory means comprising: addressable memory means having memory locations for addressably inputting, storing, retrieving and outputting said digital data; W-pointer means for addressing one of said memory locations into which said inputted digital data is to be stored; R-pointer means for addressing one of said memory locations from which said stored digital data is to be retrieved; C-pointer means for selectably addressing one of said memory locations which serves as a boundary between first and second subsets of said stored digital data within said FIFO memory means; and commitment decision means for specifying said memory location to be addressed by said C-pointer means.

Claim 4

A FIFO memory means for providing first-in, first-out digital data storage and retrieval, sequentially inputting and storing digital data and sequentially retrieving and outputting said stored digital data, said digital data having start data and end data, said FIFO memory means comprising: addressable memory means having memory locations for addressably inputting, storing, retrieving and outputting said digital data; W-pointer means for addressing one of said memory locations into which said inputted digital data is to be stored; R-pointer means for addressing one of said memory locations from which said stored digital data is to be retrieved; C-pointer means for selectably addressing one of said memory locations which serves as a boundary between first and second subsets of said stored digital data within said FIFO memory means; and commitment decision means for specifying said memory location to be addressed by said C-pointer means.

Claim 5

A FIFO memory means as recited in claim 2, said FIFO memory means further comprising EOF-flagging means for indicating whether said end data of said digital data has been stored, W-positioning means for specifying said memory location to be addressed by said W-pointer means, and R-positioning means for specifying said memory location to be addressed by said R-pointer means.

Claim 6

A FIFO memory means as recited in claim 3, wherein said EOF-flagging means comprises a digital register.

Claim 7

A FIFO memory means as recited in claim 3, wherein each of said positioning means comprises a digital register.

Claim 8

A FIFO memory means as recited in claim 2 or 3, wherein said commitment decision means compares a subset of said inputted digital data with a predefined reference set of digital data.

Claim 9

A FIFO memory means as recited in claim 4, wherein said predefined reference set of digital data is peculiar to said FIFO memory means.

Claim 10

A FIFO memory means as recited in claim 6, wherein said commitment decision means comprises a digital comparator circuit.

Claim 11

A FIFO memory means as recited in claim 2 or 3 wherein said commitment decision means comprises a digital comparator circuit.

Claim 12

A FIFO memory means as recited in claim 2, said FIFO memory means further comprising outputting means for outputting said retrieved digital data, said outputting means having states of readiness and unreadiness, and wherein said commitment decision means monitors said states of readiness and unreadiness of said outputting means.

Claim 13

A FIFO memory means as recited in claim 10, wherein said commitment decision means comprises a digital register.

Claim 14

A FIFO memory means as recited in claim 10, wherein said outputting means comprises a digital data medium.

Claim 15

A FIFO memory means as recited in claim 2, 3 or 10, wherein said addressable memory means comprises a random access memory.

Claim 16

A FIFO memory means as recited in claim 2, 3 or 7, wherein each of said pointer means comprises a digital register.

Claim 17

A first-in, first-out memory system for sequentially inputting and storing digital data and sequentially retrieving and outputting said stored digital data, said memory system comprising: a random access memory having a plurality of memory locations with individual addresses; a W-pointer register providing the address of one of said memory locations into which said inputted digital data is to be stored; an R-pointer register providing the address of one of said memory locations from which said stored digital data is to be retrieved; a C-pointer register providing the address of one of said memory locations which is to serve as a boundary between first and second subsets of said stored digital data within said first-in, first-out memory system; and a comparator coupled to receive said inputted digital data and to compare a preselectable subset of said inputted digital data with a predefined reference set of digital data, and further coupled to provide a comparison signal indicative of whether said subset of inputted digital data matches said predefined reference set of digital data, wherein said addresses provided by said pointer registers are selectively responsive to said comparison signal.

Claim 18

A first-in, first-out memory system for sequentially inputting and storing digital data and sequentially retrieving and outputting said stored digital data, said memory system comprising: a random access memory having a plurality of memory locations with individual addresses; a W-pointer register providing the address of one of said memory locations into which said inputted digital data is to be stored; an R-pointer register providing the address of one of said memory locations from which said stored digital data is to be retrieved; a C-pointer register providing the address of one of said memory locations which is to serve as a boundary between first and second subsets of said stored digital data within said first-in, first-out memory system; and a comparator coupled to receive said inputted digital data and to compare a preselectable subset of said inputted digital data with a predefined reference set of digital data, and further coupled to provide a comparison signal indicative of whether said subset of inputted digital data matches said predefined reference set of digital data, wherein said addresses provided by said pointer registers are selectively responsive to said comparison signal.

Claim 19

A first-in, first-out memory system as recited in claim 15, wherein said predefined reference set of digital data is peculiar to said first-in, first-out memory system.

Claim 20

A first-in, first-out memory system for sequentially inputting and storing digital data and sequentially retrieving and outputting said stored digital data, said memory system comprising: a random access memory having a plurality of memory locations with individual addresses; a W-pointer register providing the address of one of said memory locations into which said inputted digital data is to be stored; an R-pointer register providing the address of one of said memory locations from which said stored digital data is to be retrieved; a C-pointer register providing the address of one of said memory locations which is to serve as a boundary between first and second subsets of said stored digital data within said first-in, first-out memory system; a data medium onto which said retrieved data is outputted, said data medium having states of readiness and unreadiness; and a digital register coupled to receive a readiness status signal indicative of said states of readiness and unreadiness of said data medium, and further coupled to provide a readiness signal indicative of whether said data medium is ready to accept said retrieved digital data, wherein said addresses provided by said pointer registers are selectively responsive to said readiness signal.

Claim 21

A first-in, first-out memory system for sequentially inputting and storing digital data and sequentially retrieving and outputting said stored digital data, said memory system comprising: a random access memory having a plurality of memory locations with individual addresses; a W-pointer register providing the address of one of said memory locations into which said inputted digital data is to be stored; an R-pointer register providing the address of one of said memory locations from which said stored digital data is to be retrieved; a C-pointer register providing the address of one of said memory locations which is to serve as a boundary between first and second subsets of said stored digital data within said first-in, first-out memory system; a data medium onto which said retrieved data is outputted, said data medium having states of readiness and unreadiness; and a digital register coupled to receive a readiness status signal indicative of said states of readiness and unreadiness of said data medium, and further coupled to provide a readiness signal indicative of whether said data medium is ready to accept said retrieved digital data, wherein said addresses provided by said pointer registers are selectively responsive to said readiness signal.

Claim 22

A data interface system for inputting and storing digital data received from a shared data medium, said data interface system comprising: a random access memory having a plurality of memory locations with individual addresses; a W-pointer register providing the address of one of said memory locations into which said inputted digital data is to be stored; an R-pointer register providing the address of one of said memory locations from which said stored digital data is to be retrieved; a C-pointer register providing the address of one of said memory locations which is to serve as a boundary between first and second subsets of said stored digital data within said data interface system; and a comparator coupled to receive said inputted digital data and to compare a preselectable subset of said inputted digital data with a predefined reference set of digital data, and further coupled to provide a comparison signal indicative of whether said subset of inputted digital data matches said predefined reference set of digital data, wherein said addresses provided by said pointer registers are selectively responsive to said comparison signal.

Claim 23

A data interface system for inputting and storing digital data received from a shared data medium, said data interface system comprising: a random access memory having a plurality of memory locations with individual addresses; a W-pointer register providing the address of one of said memory locations into which said inputted digital data is to be stored; an R-pointer register providing the address of one of said memory locations from which said stored digital data is to be retrieved; a C-pointer register providing the address of one of said memory locations which is to serve as a boundary between first and second subsets of said stored digital data within said data interface system; and a comparator coupled to receive said inputted digital data and to compare a preselectable subset of said inputted digital data with a predefined reference set of digital data, and further coupled to provide a comparison signal indicative of whether said subset of inputted digital data matches said predefined reference set of digital data, wherein said addresses provided by said pointer registers are selectively responsive to said comparison signal.

Claim 24

A data interface system as recited in claim 18, wherein said predefined reference set of digital data is peculiar to said data interface system.

Claim 25

A data interface system for storing, retrieving and outputting digital data onto a shared data medium, said shared data medium having states of readiness and unreadiness with respect to the availability of said data medium to accept said digital data from said data interface system, said data interface system comprising: a random access memory having a plurality of memory locations with individual addresses; a W-pointer register providing the address of one of said memory locations into which said digital data is to be stored; an R-pointer register providing the address of one of said memory locations from which said stored digital data is to be retrieved; a C-pointer register providing the address of one of said memory locations which is to serve as a boundary between first and second subsets of said stored digital data within said data interface system; and a digital register coupled to receive a readiness status signal indicative of said states of readiness and unreadiness of said shared data medium, and further coupled to provide a readiness signal indicative of whether said shared data medium is ready to accept said retrieved digital data, wherein said addresses provided by said pointer registers are selectively responsive to said readiness signal.

Claim 26

A data interface system for storing, retrieving and outputting digital data onto a shared data medium, said shared data medium having states of readiness and unreadiness with respect to the availability of said data medium to accept said digital data from said data interface system, said data interface system comprising: a random access memory having a plurality of memory locations with individual addresses; a W-pointer register providing the address of one of said memory locations into which said digital data is to be stored; an R-pointer register providing the address of one of said memory locations from which said stored digital data is to be retrieved; a C-pointer register providing the address of one of said memory locations which is to serve as a boundary between first and second subsets of said stored digital data within said data interface system; and a digital register coupled to receive a readiness status signal indicative of said states of readiness and unreadiness of said shared data medium, and further coupled to provide a readiness signal indicative of whether said shared data medium is ready to accept said retrieved digital data, wherein said addresses provided by said pointer registers are selectively responsive to said readiness signal.