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US5675589A
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Programmable scan chain testing structure and method
Assignee: Xilinx Inc
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Filing: 1996-04-30
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Granted: 1997-10-07
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Expires: 2016-04-30
Abstract
Abstract A circuit and method for testing Field Programmable Gate Arrays (FPGAs) comprises a programmable multiplexer for sequentially connecting columns of logic cells to enable the configuring of logic cell columns into one or more scan chains. Each column of logic cells contains an edge cell comprising a multi-input multiplexer, one of the multiplexer inputs being dedicated to receiving a signal from an adjacent cell, other of the inputs being connected to gate array input pads. A programmable control signal on the multiplexer enables the column to either receive test data from one of the gate array input pads or to connect as part of a scan chain by receiving a wrapping signal from the output logic cell of an adjacent column.
Inventors
- 👤 Wilson K. Yee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:02
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318516; G01R31/318519; G01R31/318533; G01R31/318536; G01R31/318572
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
123 words
A circuit for scan chain testing a plurality of logic cells, the circuit comprising: a first set of logic cells having a first input terminal, a first output terminal, and linked logic cells; a second set of logic cells having a second input terminal, a second output terminal, and linked logic cells; a selection means coupled to the first set of logic cells for selectively propagating a first test signal to the first input terminal of the first set of logic cells, wherein the selection means is programmably controlled; and routing means coupled to the selection means for routing a second test signal from the second output terminal of the second set of logic cells to an input terminal of the selection means.
Claim 2
Dependent Claim
123 words
A circuit for scan chain testing a plurality of logic cells, the circuit comprising: a first set of logic cells having a first input terminal, a first output terminal, and linked logic cells; a second set of logic cells having a second input terminal, a second output terminal, and linked logic cells; a selection means coupled to the first set of logic cells for selectively propagating a first test signal to the first input terminal of the first set of logic cells, wherein the selection means is programmably controlled; and routing means coupled to the selection means for routing a second test signal from the second output terminal of the second set of logic cells to an input terminal of the selection means.
Claim 3
Dependent Claim
39 words
The circuit according to claim 1, further comprising a second selection means coupled to the second set of logic cells for selectively propagating a third test signal to the second input terminal of the second set of logic cells.
Claim 4
Dependent Claim
20 words
The circuit according to claim 1, wherein the routing means further enables transmission of test data to an output pad.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-06 | 2001-04-07 | 2001-10-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-06 | 2005-04-07 | 2005-10-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-06 | 2009-04-07 | 2009-10-07 | $7700.00 | Window Closed / Lapsed |