US4931671A
Expired / Lapsed
US
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Multiple array customizable logic device
Assignee: Lattice Semiconductor Corp
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Filing: 1988-04-07
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Granted: 1990-06-05
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Expires: 2008-04-07
Abstract
Abstract Disclosed is an integrated circuit having multiple programmable arrays providing customizable logic. The integrated circuit has at least a first programmable array receiving a plurality of first inputs and generating a plurality of first outputs as programmed by the user. Also, it includes a second programmable array receiving a plurality of second inputs and generating a plurality of second outputs as programmed by the user. A means for selectiving interconnecting the inputs and outputs from the first and second programmable arrays is provided so that the programmable signals generated can be selectively connected in series, in parallel, or in a combination of series and parallel. Also provided are buried state registers for storing signals as programmed by the user. The stored signals from the buried state registers are likewise selectively interconnected with the input signals and output signals to provide added flexibility and power for the logic designer utilizing the device of the present invention.
Inventors
- 👤 Om Agrawal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:22
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
267 words
An integrated circuit having customizable logic, comprising: first programmable array means having a first plurality of input lines and a first plurality of output lines wherein said first programmable array means receives a plurality of first input terms from said first plurality of input lines and generates a plurality of first output terms on said first plurality of output lines; second programmable array means having a second plurality of input lines and a second plurality of output lines wherein said second programmable array means receives a plurality of second input terms from said second plurality of input lines and generates a plurality of second output terms on said second plurality of output lines; and means, operatively coupled to said first programmable array means and said second programmable array means, for selectively interconnecting said plurality of first input lines, said plurality of first output lines, said plurality of second input lines, and said plurality of second output lines wherein: said interconnect means selectively couples each of said first plurality of output lines to each of said first plurality of input lines and said second plurality of input lines so that each of said first plurality of output terms are operatively couplable to each of said first and said second pluralities of input lines; and said interconnect means selectively couples each of said second plurality of output lines to each of said first plurality of input lines and said second plurality of input lines so that each of said second plurality of output terms are operatively couplable to each of said first and said second pluralities of input lines.
Claim 2
Dependent Claim
267 words
An integrated circuit having customizable logic, comprising: first programmable array means having a first plurality of input lines and a first plurality of output lines wherein said first programmable array means receives a plurality of first input terms from said first plurality of input lines and generates a plurality of first output terms on said first plurality of output lines; second programmable array means having a second plurality of input lines and a second plurality of output lines wherein said second programmable array means receives a plurality of second input terms from said second plurality of input lines and generates a plurality of second output terms on said second plurality of output lines; and means, operatively coupled to said first programmable array means and said second programmable array means, for selectively interconnecting said plurality of first input lines, said plurality of first output lines, said plurality of second input lines, and said plurality of second output lines wherein: said interconnect means selectively couples each of said first plurality of output lines to each of said first plurality of input lines and said second plurality of input lines so that each of said first plurality of output terms are operatively couplable to each of said first and said second pluralities of input lines; and said interconnect means selectively couples each of said second plurality of output lines to each of said first plurality of input lines and said second plurality of input lines so that each of said second plurality of output terms are operatively couplable to each of said first and said second pluralities of input lines.
Claim 3
Dependent Claim
241 words
A customizable logic circuit formed on a single integrated circuit chip, comprising: first programmable array means for receiving a plurality of first input terms and generating a plurality of first output terms including at least one programmable array generating first logic output terms; second programmable array means for receiving a plurality of second input terms and generating a plurality of second output terms including at least one programmable array generating second logic output terms; at least one buried state register, operatively connected to receive at least one logic output term from one of said first programmable array means and said second programmable array means, for storing a logic term and for supplying the stored logic term; input multiplexing means, responsive to an input select signal, for selecting and supplying a set of signals as said plurality of first input terms and said plurality of second input terms from a plurality of signals, including said plurality of first output terms, said plurality of second output terms, said stored logic term, and a plurality of input signals externally supplied to the integrated circuit chip; means for supplying said input select signal; output multiplexing means, responsive to an output select signal, for selecting and supplying a set of signals as output signals from a plurality of signals including at least a subset of said plurality of first output terms and said plurality of second output terms; and means for supplying said output select signal.
Claim 4
Dependent Claim
241 words
A customizable logic circuit formed on a single integrated circuit chip, comprising: first programmable array means for receiving a plurality of first input terms and generating a plurality of first output terms including at least one programmable array generating first logic output terms; second programmable array means for receiving a plurality of second input terms and generating a plurality of second output terms including at least one programmable array generating second logic output terms; at least one buried state register, operatively connected to receive at least one logic output term from one of said first programmable array means and said second programmable array means, for storing a logic term and for supplying the stored logic term; input multiplexing means, responsive to an input select signal, for selecting and supplying a set of signals as said plurality of first input terms and said plurality of second input terms from a plurality of signals, including said plurality of first output terms, said plurality of second output terms, said stored logic term, and a plurality of input signals externally supplied to the integrated circuit chip; means for supplying said input select signal; output multiplexing means, responsive to an output select signal, for selecting and supplying a set of signals as output signals from a plurality of signals including at least a subset of said plurality of first output terms and said plurality of second output terms; and means for supplying said output select signal.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 1993-06-04 | 1993-12-04 | 1994-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-04 | 1997-12-04 | 1998-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-04 | 2001-12-04 | 2002-06-05 | $7700.00 | Window Closed / Lapsed |