Flexible configuration logic array block for programmable logic devices

Claim 2

A logic array block comprising: a plurality of logic signal conductors capable of being programmably connected to external conductors; a plurality of dedicated global control input conductors originating outside the logic array block; a plurality of local feedback conductors; a plurality of local control input conductors; a programmable configuration array for programmably connecting any of the logic signal conductors, the global control input conductors, and the local feedback conductors to any of the local control input conductors; and a plurality of programmable macrocells capable of performing multi-variable logic functions, each macrocell comprising: a plurality of macrocell input terminals capable of being programmably connected to any of the logic signal conductors and the local feedback conductors, programmable combinatorial logic circuitry connected to the macrocell input terminals for generating a logic result, means for gating the logic result, the gating means being connected to the combinatorial logic circuitry, and having a plurality of control input terminals and an output terminal, a programmable control array for programmably connecting any of the control input terminals to any of the local control input conductors, and a macrocell output terminal connected to the gating means output terminal, one of the local feedback conductors, and one of the external conductors.

Claim 3

A logic array block as described in claim 1, further comprising: a first array of programmable switches by which the logic signal conductors are capable of being programmably connected to the external conductors; a second array of programmable switches by which the logic signal conductors, the global control input conductors, and the local feedback conductors are programmably connected to any of the local control input conductors; a third array of programmable switches by which the logic signal conductors and the local feedback conductors are programmably connected to the macrocell input terminals; and a fourth array of programmable switches by which the control input terminals are programmably connected to the local control input conductors.

Claim 4

A logic array block as described in claim 2 wherein the programmable switches comprise programmable multiplexers.

Claim 5

A logic array block as described in claim 2, further comprising a plurality of memory cells which control the first, second, third, and fourth array of programmable switches.

Claim 6

A logic array block as described in claim 4 wherein the memory cells comprise static random-access memory cells.

Claim 7

A logic array block as described in claim 1 wherein the combinatorial logic circuitry comprises at least one programmable look-up table.

Claim 8

A logic array block as described in claim 1 wherein the gating means comprises a D-type flip-flop.

Claim 9

A logic array block as described in claim 7 further comprising a means of bypassing the D-type flip-flop.

Claim 10

A logic array block for use in a programmable logic device architecture, the logic array block comprising: a plurality of logic signal conductors; a plurality of dedicated global control input conductors originating outside the logic array block; a plurality of local feedback conductors; a plurality of local control input conductors; a plurality of macrocell input conductors; a first array of programmable switches; a second array of programmable switches; a third array of programmable switches; a programmable interface for programmably connecting the logic signal conductors to external conductors by means of the first array of programmable switches; a programmable configuration array for programmably connecting any of the logic signal conductors, the global control input conductors, and the local feedback conductors to any of the local control input conductors by means of the second array of programmable switches; a programmable main interconnect array for programmably connecting any of the logic signal conductors and the local feedback conductors to any of the macrocell input conductors by means of the third array of programmable switches; a plurality of programmable macrocells capable of performing multi-variable logic functions, each macrocell comprising: a plurality of macrocell input terminals, each macrocell input terminal connected to one of the macrocell input conductors, programmable combinatorial logic circuitry connected to the macrocell input terminals for generating a logic result, the combinatorial logic circuitry having an output terminal, means for gating the logic result connected to the combinatorial logic circuitry output terminal, the gating means having a plurality of control input terminals and an output terminal, a fourth array of programmable switches for programmably connecting any of the control input terminals to any of the local control input conductors, a macrocell output terminal connected to the gating means output terminal, one of the local feedback conductors, and one of the external conductors, an allocation input terminal connected to the combinatorial logic circuitry, and an allocation output terminal connected to the combinatorial logic circuitry output terminal; a plurality of allocation signal conductors, each of the allocation signal conductors being connected between the allocation output terminal of one of the programmable macrocells and the allocation input terminal of an adjacent programmable macrocell; a plurality of buffer/driver circuits in series with the local control input conductors, the local feedback conductors, and the logic signal conductors; and a plurality of memory cells for controlling the first, second, third, and fourth arrays of programmable switches.

Claim 11

A logic array block for use in a programmable logic device architecture, the logic array block comprising: a plurality of logic signal conductors; a plurality of dedicated global control input conductors originating outside the logic array block; a plurality of local feedback conductors; a plurality of local control input conductors; a plurality of macrocell input conductors; a first array of programmable switches; a second array of programmable switches; a third array of programmable switches; a programmable interface for programmably connecting the logic signal conductors to external conductors by means of the first array of programmable switches; a programmable configuration array for programmably connecting any of the logic signal conductors, the global control input conductors, and the local feedback conductors to any of the local control input conductors by means of the second array of programmable switches; a programmable main interconnect array for programmably connecting any of the logic signal conductors and the local feedback conductors to any of the macrocell input conductors by means of the third array of programmable switches; a plurality of programmable macrocells capable of performing multi-variable logic functions, each macrocell comprising: a plurality of macrocell input terminals, each macrocell input terminal connected to one of the macrocell input conductors, programmable combinatorial logic circuitry connected to the macrocell input terminals for generating a logic result, the combinatorial logic circuitry having an output terminal, means for gating the logic result connected to the combinatorial logic circuitry output terminal, the gating means having a plurality of control input terminals and an output terminal, a fourth array of programmable switches for programmably connecting any of the control input terminals to any of the local control input conductors, a macrocell output terminal connected to the gating means output terminal, one of the local feedback conductors, and one of the external conductors, an allocation input terminal connected to the combinatorial logic circuitry, and an allocation output terminal connected to the combinatorial logic circuitry output terminal; a plurality of allocation signal conductors, each of the allocation signal conductors being connected between the allocation output terminal of one of the programmable macrocells and the allocation input terminal of an adjacent programmable macrocell; a plurality of buffer/driver circuits in series with the local control input conductors, the local feedback conductors, and the logic signal conductors; and a plurality of memory cells for controlling the first, second, third, and fourth arrays of programmable switches.

Claim 12

A logic array block as described in claim 9 wherein the programmable switches comprise programmable multiplexers.

Claim 13

A logic array block as described in claim 9 wherein the memory cells comprise static random-access memory cells embedded in the programmable logic device.

Claim 14

A logic array block as described in claim 9 wherein the combinatorial logic circuitry comprises at least one programmable look-up table.

Claim 15

A logic array block as described in claim 9 wherein the gating means comprises a D-type flip-flop.

Claim 16

A logic array block as described in claim 13 further comprising a means of bypassing the D-type flip-flop.

Claim 17

A logic array block for use in a programmable logic device architecture, the logic array block comprising: thirty-six logic signal conductors; eight global control input conductors originating outside the logic array block; sixteen local feedback conductors; a plurality of local control input conductors; a plurality of macrocell input conductors; a first array of programmable multiplexers; a second array of programmable multiplexers; a third array of programmable multiplexers; a programmable interface for programmably connecting the logic signal conductors to external conductors by means of the first array of programmable multiplexers; a programmable configuration array for programmably connecting any of the logic signal conductors, the global control input conductors, and the local feedback conductors to any of the local control input conductors by means of the second array of programmable multiplexers; a programmable main interconnect array for programmably connecting any of the logic signal conductors and the local feedback conductors to any of the macrocell input conductors by means of the third array of programmable multiplexers; sixteen programmable macrocells capable of performing multi-variable logic functions, each macrocell comprising: a plurality of macrocell input terminals, each macrocell input terminal connected to one of the macrocell input conductors, at least one four-input programmable look-up table connected to the macrocell input terminals for generating a look-up table output, each look-up table having an output terminal, means for combining look-up table outputs to produce a logic result, the combining means having a plurality of input terminals and an output terminal, each look-up table output terminal being connected to a combining means input terminal, means for gating the logic result, the gating means being connected to the combining means output terminal, and having a plurality of control input terminals and an output terminal, a fourth array of programmable multiplexers for programmably connecting any of the control input terminals to any of the local control input conductors, a macrocell output terminal connected to the gating means output terminal, one of the local feedback conductors, and one of the external conductors, an allocation input terminal connected to a combining means input terminal, and an allocation output terminal connected to the combining means output terminal; a plurality of allocation signal conductors, each of the allocation signal conductors being connected between the allocation output terminal of one of the programmable macrocells and the allocation input terminal of an adjacent programmable macrocell; a plurality of buffer/driver circuits in series with the local control input conductors, the local feedback conductors, and the logic signal conductors; and a plurality of static random-access memory cells embedded in the programmable logic device for controlling the first, second, third, and fourth arrays of multiplexers.

Claim 18

A logic array block for use in a programmable logic device architecture, the logic array block comprising: thirty-six logic signal conductors; eight global control input conductors originating outside the logic array block; sixteen local feedback conductors; a plurality of local control input conductors; a plurality of macrocell input conductors; a first array of programmable multiplexers; a second array of programmable multiplexers; a third array of programmable multiplexers; a programmable interface for programmably connecting the logic signal conductors to external conductors by means of the first array of programmable multiplexers; a programmable configuration array for programmably connecting any of the logic signal conductors, the global control input conductors, and the local feedback conductors to any of the local control input conductors by means of the second array of programmable multiplexers; a programmable main interconnect array for programmably connecting any of the logic signal conductors and the local feedback conductors to any of the macrocell input conductors by means of the third array of programmable multiplexers; sixteen programmable macrocells capable of performing multi-variable logic functions, each macrocell comprising: a plurality of macrocell input terminals, each macrocell input terminal connected to one of the macrocell input conductors, at least one four-input programmable look-up table connected to the macrocell input terminals for generating a look-up table output, each look-up table having an output terminal, means for combining look-up table outputs to produce a logic result, the combining means having a plurality of input terminals and an output terminal, each look-up table output terminal being connected to a combining means input terminal, means for gating the logic result, the gating means being connected to the combining means output terminal, and having a plurality of control input terminals and an output terminal, a fourth array of programmable multiplexers for programmably connecting any of the control input terminals to any of the local control input conductors, a macrocell output terminal connected to the gating means output terminal, one of the local feedback conductors, and one of the external conductors, an allocation input terminal connected to a combining means input terminal, and an allocation output terminal connected to the combining means output terminal; a plurality of allocation signal conductors, each of the allocation signal conductors being connected between the allocation output terminal of one of the programmable macrocells and the allocation input terminal of an adjacent programmable macrocell; a plurality of buffer/driver circuits in series with the local control input conductors, the local feedback conductors, and the logic signal conductors; and a plurality of static random-access memory cells embedded in the programmable logic device for controlling the first, second, third, and fourth arrays of multiplexers.

Claim 19

A logic array block as described in claim 15 wherein the gating means comprises a D-type flip-flop.

Claim 20

A logic array block as described in claim 16 further comprising a means of bypassing the D-type flip-flop.

Claim 21

A logic array block as described in claim 15, wherein the number of 4-input look-up tables per macrocell is two, and the combining means comprises a 3-input AND gate.

Claim 22

A logic array block as described in claim 15, wherein the number of 4-input look-up tables per macrocell is two, and the combining means comprises a custom 3-input look-up table.

Claim 23

A logic array block as described in claim 15, wherein the number of 4-input look-up tables per macrocell is one, each macrocell further comprising a macrocell expander input terminal connected to one of the combining means input terminals.

Claim 24

A logic array block as described in claim 20, further comprising eight expander look-up tables, each expander look up table having four expander look-up table input terminals and an expander look-up table output terminal, the expander look-up table input terminals being connected to selected macrocell input conductors, and the expander look-up table output terminal capable of being programmably connected to any of the macrocell expander input terminals.