US5394034A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable logic array having programmable output driver drive capacity
Assignee: Siemens AG
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Filing: 1993-07-27
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Granted: 1995-02-28
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Expires: 2013-07-27
Abstract
Abstract A programmable logic array includes configurable logic cells disposed in lines and columns. Each of the logic cells has signal inputs, control inputs, at least one signal output, and an output driver circuit connected upstream of the at least one signal output. The output driver circuit has a terminal for a first and a second supply potential and is connected to at least one of the control inputs. The output driver circuit is controllable for setting its driver capacity to a level other than zero, corresponding to a signal value, by a digital signal applied to the at least one control input. Conductor tracks and switching elements for interconnecting the conductor tracks connect the at least one signal output of each of the logic cells to at least one of the signal inputs of at least another one of the logic cells.
Inventors
- 👤 Steffen Becker
- 👤 Doris Schmitt-Landsiedel
- 👤 Doris Keitel-Schulz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:05
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/017581; H03K19/02; H03K19/173; H03K19/1733
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
153 words
A programmable logic array comprising: configurable logic cells disposed in lines and columns, each of said logic cells having signal inputs, control inputs, at least one signal output, and an output driver circuit connected upstream of the at least one signal output, said output driver circuit having a terminal for a first and a second supply potential and being connected to at least one of the control inputs, and said output driver circuit being controllable for setting its driver capacity to a level other than zero, corresponding to a signal value, by means of a digital signal applied to the at least one control input; and conductor tracks and switching elements for interconnecting said conductor tracks, said switching elements and said conductor tracks connecting the at least one signal output of each of said logic cells to at least one of the signal inputs of at least another one of said logic cells.
Claim 2
Dependent Claim
153 words
A programmable logic array comprising: configurable logic cells disposed in lines and columns, each of said logic cells having signal inputs, control inputs, at least one signal output, and an output driver circuit connected upstream of the at least one signal output, said output driver circuit having a terminal for a first and a second supply potential and being connected to at least one of the control inputs, and said output driver circuit being controllable for setting its driver capacity to a level other than zero, corresponding to a signal value, by means of a digital signal applied to the at least one control input; and conductor tracks and switching elements for interconnecting said conductor tracks, said switching elements and said conductor tracks connecting the at least one signal output of each of said logic cells to at least one of the signal inputs of at least another one of said logic cells.
Claim 3
Dependent Claim
141 words
The programmable logic array according to claim 1, wherein: (a) said output driver circuit includes a control logic having one input and at least two outputs, and at least two amplifier stages to be shut off, each of said amplifier stages has one control input and one terminal for the first and second supply potential; (b) the input of said control logic is connected to the at least one control input of said logic cell, and the outputs of said control logic are each connected to a respective one of the control inputs of said amplifier stages; (c) said amplifier stages have input/output signal paths being connected in parallel; and (d) said control logic generates signals at its outputs, with which at least one of said amplifier stages is turned on and the other of said amplifier stages is turned off.
Claim 4
Dependent Claim
16 words
The programmable logic array according to claim 2, wherein said amplifier stages have different driver capacities.
Claim 5
Dependent Claim
27 words
The programmable logic array according to claim 3, wherein said at least two amplifier stages are n amplifier stages, and said control logic is a one-out-of-n decoder.
Claim 6
Dependent Claim
15 words
The programmable logic array according to claim 2, wherein said amplifier stages are tri-state stages.
Claim 7
Dependent Claim
53 words
The programmable logic array according to claim 2, wherein said output driver circuit has a terminal for an enable signal, and logic switching elements connected between said terminal for the enable signal and each of the control inputs of said amplifier stages, for jointly turning said amplifier stages off with the enable signal.
Claim 8
Dependent Claim
39 words
The programmable logic array according to claim 6, including a further amplifier stage being connected parallel to the signal paths of said amplifier stages and having a control input being connected directly to said terminal for the enable signal.
Claim 9
Dependent Claim
106 words
In a programmable logic array having configurable logic cells disposed in lines and columns, each of said logic cells comprising: signal inputs, control inputs, at least one signal output, and an output driver circuit connected upstream of the at least one signal output, said output driver circuit having a terminal for a first and a second supply potential and being connected to at least one of the control inputs, and said output driver circuit being controllable for setting its driver capacity to a level other than zero, corresponding to a signal value, by means of a digital signal applied to the at least one control input.
Claim 10
Dependent Claim
106 words
In a programmable logic array having configurable logic cells disposed in lines and columns, each of said logic cells comprising: signal inputs, control inputs, at least one signal output, and an output driver circuit connected upstream of the at least one signal output, said output driver circuit having a terminal for a first and a second supply potential and being connected to at least one of the control inputs, and said output driver circuit being controllable for setting its driver capacity to a level other than zero, corresponding to a signal value, by means of a digital signal applied to the at least one control input.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-27 | 1998-08-29 | 1999-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-27 | 2002-08-29 | 2003-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-27 | 2006-08-29 | 2007-02-28 | $7700.00 | Window Closed / Lapsed |