US5034634A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiple level programmable logic integrated circuit
Assignee: Omron Corp
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Filing: 1989-12-21
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Granted: 1991-07-23
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Expires: 2009-12-21
Abstract
Abstract A programmable logic IC comprising an input buffer segment, a programmable logic segment and an output buffer segment, the input buffer segment and output buffer segment respectively comprising buffers of a first level and buffers of a second level as disposed in parallel arrays of the two levels and whichever of the levels being optionally selectable by programming.
Inventors
- 👤 Norihito Yamamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 10:29
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/017581; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
76 words
A programmable logic integrated circuit comprising: a programmable logic segment; and an input buffer segment and an output buffer segment each connected to the logic segment, each buffer segment having a first buffer means for signals of a first level and a second buffer means for signals of a second level, the first and second buffer means in each segment being connected in parallel arrays and being optically selectable by means of programming the logic segment.
Claim 2
Dependent Claim
76 words
A programmable logic integrated circuit comprising: a programmable logic segment; and an input buffer segment and an output buffer segment each connected to the logic segment, each buffer segment having a first buffer means for signals of a first level and a second buffer means for signals of a second level, the first and second buffer means in each segment being connected in parallel arrays and being optically selectable by means of programming the logic segment.
Claim 3
Dependent Claim
18 words
A circuit according to claim 1, wherein the first level is TTL and the second level is C-MOS.
Claim 4
Dependent Claim
25 words
A circuit according to claim 1, wherein the output and input buffer segments are connected to the programmable logic segment through a plurality of transistors.
Claim 5
Dependent Claim
32 words
A circuit according to claim 1, wherein the logic segment comprises: a matrix unit having a plurality of lines and rows; a plurality OR circuits; and a plurality of exclusive OR circuits.
Claim 6
Dependent Claim
24 words
A circuit according to claim 3, wherein the transistors are positioned at each junction of a line and a row of the matrix unit.
Claim 7
Independent Claim
215 words
A method of programming a programmable logic integrated circuit for selectively interfacing with peripherals of different levels comprising: a) providing a programmable logic integrated circuit comprising: a programmable logic circuit comprising a matrix unit formed by a plurality of lines and rows, OR circuits; and exclusive OR circuits; and an input buffer segment and an output buffer segment connected to the logic segment, each buffer segment having a first buffer means for signals of a first level and a second buffer means for signals of a second level, the first and second buffer means in each segment being connected in parallel arrays and being optimally selected by means of programming the logic segment; b) selecting a peripheral input device having signals compatible with one of the first or second levels; c) disconnecting a plurality of transistors connecting the peripheral input device to the input buffer means for signals of the other level of the input buffer segment; d) receiving an input through the buffer means compatible with the peripheral input signals; e) disconnecting a plurality of transistors connecting the buffer means compatible with signals of the other level of the output buffer segment; and f) sending the output to a peripheral output device through the buffers means compatible with signal levels of the peripheral output.
Claim 8
Independent Claim
215 words
A method of programming a programmable logic integrated circuit for selectively interfacing with peripherals of different levels comprising: a) providing a programmable logic integrated circuit comprising: a programmable logic circuit comprising a matrix unit formed by a plurality of lines and rows, OR circuits; and exclusive OR circuits; and an input buffer segment and an output buffer segment connected to the logic segment, each buffer segment having a first buffer means for signals of a first level and a second buffer means for signals of a second level, the first and second buffer means in each segment being connected in parallel arrays and being optimally selected by means of programming the logic segment; b) selecting a peripheral input device having signals compatible with one of the first or second levels; c) disconnecting a plurality of transistors connecting the peripheral input device to the input buffer means for signals of the other level of the input buffer segment; d) receiving an input through the buffer means compatible with the peripheral input signals; e) disconnecting a plurality of transistors connecting the buffer means compatible with signals of the other level of the output buffer segment; and f) sending the output to a peripheral output device through the buffers means compatible with signal levels of the peripheral output.
References Cited (Backward Citations)
US4527079A
Cited
US4710842A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-22 | 1995-01-21 | 1995-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-22 | 1999-01-21 | 1999-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-22 | 2003-01-21 | 2003-07-23 | $7700.00 | Window Closed / Lapsed |