High-density erasable programmable logic device architecture using multiplexer interconnections

Claim 2

A programmable logic device for producing a plurality of first signals, each of which is a programmable logic function of a plurality of second signals, the programmable logic device comprising: a plurality of logic array blocks, each of which has a plurality of inputs and at least one output with each output carrying a respective one of the plurality of first signals; a plurality of global conductors, each global conductor being fed by a respective one of the plurality of second signals; a plurality of first multiplexers, each of which has a plurality of inputs with each input being connected to a respective one of the global conductors, and an output; and a plurality of second multiplexers, each of which has a plurality of inputs with each input being connected to the output of a uniquely respective one of the first multiplexers, and an output connected to the input of a respective one of the logic array blocks, wherein each of the global conductors has two unique paths through two different first multiplexers to a single logic array block and each global conductor also has two unique paths from each one of the first multiplexers through two different second multiplexers to two different logic array blocks.

Claim 3

The programmable logic device of claim 1 wherein each global conductor carries a signal and each one of the plurality of first multiplexers can be programmed to select one of the signals on the global conductors connected to its inputs to be transferred to its output.

Claim 4

The programmable logic device of claim 2 wherein each output of the plurality of logic array blocks is connected to a respective one of the global conductors, the connections from logic array block outputs to global conductors form a specific pattern, and the outputs of each logic array block are partitioned into at least one group.

Claim 5

The programmable logic device of claim 3 wherein, in the specific pattern, the universe of first multiplexers fed by any one global conductor differs from the universe of first multiplexers fed by any other global conductor.

Claim 6

The programmable logic device of claim 3 wherein, in the specific pattern, any two inputs of any first multiplexer are connected to global conductors in different groups.

Claim 7

The programmable logic device of claim 3 wherein, in the specific pattern, the global conductors in any two groups from different logic array blocks together with the first multiplexers to whose inputs they are connected and the second multiplexers to which the outputs of the first multiplexers are connected form an acyclic chain.

Claim 8

The programmable logic device of claim 3 wherein the signals on the global conductors connected to the inputs of the plurality of first multiplexers are selected for transfer to the outputs of the second multiplexers by successively attempting to assign each global conductor to an output of one of the second multiplexers to which the global conductor is essentially connected in accordance with the specific pattern until all second multiplexer outputs are assigned, or until all possible assignments have been attempted.

Claim 9

The programmable logic device of claim 7 wherein each successive attempt attempts to assign each global conductor to an output of one of the second multiplexers to which the global conductor is essentially connected in the specific pattern using a procedure which operates recursively by: switching a first one of the first multiplexers to propagate signals from a first global conductor to the output of a first one of the second multiplexers if the first one of the first multiplexers has not been switched to propagate signals from any other global conductor to the output of the first one of the second multiplexers and the first one of the second multiplexers has not been switched to propagate signals from any other global conductor; or if a second global conductor has already been assigned to the output of the first one of the first multiplexers, by attempting to assign the first global conductor to a second one of the first multiplexers and a second one of the second multiplexers; or if the first one of the second multiplexers has already been assigned to the output of one of the first multiplexers, by attempting to assign the first global conductor to a second one of the first multiplexers and a second one of the second multiplexers.

Claim 10

The programmable logic device of claim 1 further comprising input and output pads controlled by tri-state buffers having means for programmatically controlling output voltage slew rate.

Claim 11

The programmable logic device of claim 1 wherein the logic array blocks further comprise macrocells and spare macrocells, the logic array blocks having means for replacing defective macrocells with spare macrocells.

Claim 12

The programmable logic device of claim 1 wherein the logic array blocks further comprise a plurality of word lines and a plurality of spare word lines, the logic array blocks having means for replacing defective word lines with spare word lines.

Claim 13

The programmable logic device of claim 1 further comprising a plurality of logical elements wherein the logical state of each logical element can be set to a desired state by connecting the logical elements in a serial arrangement having a first element whose state can be controlled and by passing a logical state string sequentially into the first element and through the serial arrangement until the desired state is obtained in each logical element.

Claim 14

The programmable logic device of claim 1 further comprising a plurality of logical elements wherein the logical state of each logical element can be monitored by connecting the logical elements in a serial arrangement having a last element whose state can be monitored such that the logical states of the logical elements form a logical state string, sequential passing the logical state string through the serial arrangement, and monitoring the logical state of the last element in the serial arrangement.

Claim 15

In a programmable logic device, a method for producing a plurality of first signals, each of which is a programmable logic function of a plurality of second signals, the method comprising the steps of: providing a plurality of logic array blocks, each of which has a plurality of inputs and a plurality of outputs with each output carrying a respective one of the plurality of first signals; providing a plurality of global conductors; providing a plurality of first multiplexers, each of which has a plurality of inputs and an output; providing a plurality of second multiplexers, each of which has a plurality of inputs and an output; feeding each one of the plurality of second signals to a respective one of the plurality of global conductors; connecting each one of the inputs of the plurality of first multiplexers to at least a respective one of the plurality of global conductors; connecting each one of the outputs of the plurality of first multiplexers to a respective input of at least two of the plurality of second multiplexers, such that each of the plurality of first multiplexers is coupled to two different logic array blocks; and connecting each one of the outputs of the plurality of second multiplexers to a respective one of the inputs of the plurality of logic array blocks.

Claim 16

In a programmable logic device, a method for producing a plurality of first signals, each of which is a programmable logic function of a plurality of second signals, the method comprising the steps of: providing a plurality of logic array blocks, each of which has a plurality of inputs and a plurality of outputs with each output carrying a respective one of the plurality of first signals; providing a plurality of global conductors; providing a plurality of first multiplexers, each of which has a plurality of inputs and an output; providing a plurality of second multiplexers, each of which has a plurality of inputs and an output; feeding each one of the plurality of second signals to a respective one of the plurality of global conductors; connecting each one of the inputs of the plurality of first multiplexers to at least a respective one of the plurality of global conductors; connecting each one of the outputs of the plurality of first multiplexers to a respective input of at least two of the plurality of second multiplexers, such that each of the plurality of first multiplexers is coupled to two different logic array blocks; and connecting each one of the outputs of the plurality of second multiplexers to a respective one of the inputs of the plurality of logic array blocks.

Claim 17

For use in a programmable logic device for producing a plurality of first signals with each of the first signals being a programmable logic function of a plurality of second signals, the programmable logic device comprising a plurality of logic array blocks with each logic array block having a plurality of inputs and a plurality of outputs with each output carrying a respective one of the plurality of first signals, a plurality of global conductors, with each global conductor being fed by a respective one of the plurality of second signals, a plurality of programmable first multiplexers and a plurality of programmable second multiplexers with each multiplexer having a plurality of inputs and an output with the inputs of the plurality of first multiplexers being connected to the plurality of global connectors in a specific interconnection pattern and the output of each of the plurality of first multiplexers being connected to one of the inputs of the plurality of second multiplexers and the output of each of the plurality of second multiplexers being connected to the input of a respective one of the logic array blocks, a system for assigning each one of the plurality of second signals to a respective logic array block input, the system comprising: means for obtaining the specific interconnection pattern; and means for selecting signals on the global conductors connected to the inputs of the plurality of first multiplexers for transfer to the outputs of the plurality of second multiplexers, said selecting means comprising means for successively attempting to assign each global conductor to a first multiplexer to which the global conductor is connected in accordance with the specific interconnection pattern until all multiplexers have been assigned, or until all possible assignments have been attempted.

Claim 18

For use in a programmable logic device for producing a plurality of first signals with each of the first signals being a programmable logic function of a plurality of second signals, the programmable logic device comprising a plurality of logic array blocks with each logic array block having a plurality of inputs and a plurality of outputs with each output carrying a respective one of the plurality of first signals, a plurality of global conductors, with each global conductor being fed by a respective one of the plurality of second signals, a plurality of programmable first multiplexers and a plurality of programmable second multiplexers with each multiplexer having a plurality of inputs and an output with the inputs of the plurality of first multiplexers being connected to the plurality of global connectors in a specific interconnection pattern and the output of each of the plurality of first multiplexers being connected to one of the inputs of the plurality of second multiplexers and the output of each of the plurality of second multiplexers being connected to the input of a respective one of the logic array blocks, a system for assigning each one of the plurality of second signals to a respective logic array block input, the system comprising: means for obtaining the specific interconnection pattern; and means for selecting signals on the global conductors connected to the inputs of the plurality of first multiplexers for transfer to the outputs of the plurality of second multiplexers, said selecting means comprising means for successively attempting to assign each global conductor to a first multiplexer to which the global conductor is connected in accordance with the specific interconnection pattern until all multiplexers have been assigned, or until all possible assignments have been attempted.

Claim 19

The system of claim 15 wherein the successive attempting means attempts to assign each global conductor to an output of one of the second multiplexers to which the global conductor is essentially connected in the specific pattern using a procedure which operates recursively by: switching a first one of the first multiplexers to propagate signals from a first global conductor to the output of the first one of the first multiplexers if the first one of the first multiplexers has not been switched to propagate signals from any other global conductor to the output of a first one of the second multiplexers; or if a second global conductor has already been assigned to the output of the first one of the first multiplexers, by attempting to assign the first global conductor to a second one of the first multiplexers and a second one of the second multiplexers; or if the first one of the second multiplexers has already been assigned to the output of one of the first multiplexers, by attempting to assign the first global conductor to a second one of the first multiplexers and a second one of the second multiplexers.

Claim 20

For use in a programmable logic device for producing a plurality of first signals with each of the first signals being a programmable logic function of a plurality of second signals, the programmable logic device comprising a plurality of logic array blocks with each logic array block having a plurality of inputs and a plurality of outputs with each output carrying a respective one of the plurality of first signals, a plurality of global conductors, with each global conductor being fed by a respective one of the plurality of second signals, a plurality of programmable first multiplexers and a plurality of programmable second multiplexers with each multiplexer having a plurality of inputs, such that the inputs of the plurality of first multiplexers are connected to the plurality of global conductors in a specific interconnection pattern and each output of the plurality of first multiplexers is connected to an input of at least two of the plurality of second multiplexers and the output of each of the plurality of second multiplexers is connected to the input of a respective one of the logic array blocks, a method for assigning each one of the plurality of second signals to a respective logic array block input, the method comprising the steps of: obtaining the specific interconnection pattern; and selecting signals on the global conductors connected to the inputs of the plurality of first multiplexers for transfer to the outputs of the second multiplexers by successively attempting to assign each global conductor to one of the plurality of first multiplexers to which the global conductor is connected in accordance with the specific interconnection pattern until all multiplexers have been assigned, or until all possible assignments have been attempted.

Claim 21

For use in a programmable logic device for producing a plurality of first signals with each of the first signals being a programmable logic function of a plurality of second signals, the programmable logic device comprising a plurality of logic array blocks with each logic array block having a plurality of inputs and a plurality of outputs with each output carrying a respective one of the plurality of first signals, a plurality of global conductors, with each global conductor being fed by a respective one of the plurality of second signals, a plurality of programmable first multiplexers and a plurality of programmable second multiplexers with each multiplexer having a plurality of inputs, such that the inputs of the plurality of first multiplexers are connected to the plurality of global conductors in a specific interconnection pattern and each output of the plurality of first multiplexers is connected to an input of at least two of the plurality of second multiplexers and the output of each of the plurality of second multiplexers is connected to the input of a respective one of the logic array blocks, a method for assigning each one of the plurality of second signals to a respective logic array block input, the method comprising the steps of: obtaining the specific interconnection pattern; and selecting signals on the global conductors connected to the inputs of the plurality of first multiplexers for transfer to the outputs of the second multiplexers by successively attempting to assign each global conductor to one of the plurality of first multiplexers to which the global conductor is connected in accordance with the specific interconnection pattern until all multiplexers have been assigned, or until all possible assignments have been attempted.

Claim 22

The method of claim 17 wherein the successive attempting step attempts to assign each global conductor to an output of one of the plurality of second multiplexers to which the global conductor is essentially connected in the specific pattern using a procedure which operates recursively by: switching a first one of the first multiplexers to propagate signals from a first global conductor to the output of a first one of the second multiplexers if the first one of the first multiplexers has not been switched to propagate signals from any other global conductor to the output of the first one of the second multiplexers; or if a second global conductor has already been assigned to the output of the first one of the first multiplexers, by attempting to assign the first global conductor to a second one of the first multiplexers and a second one of the second multiplexers; or if the first one of the second multiplexers has already been assigned to the output of one of the first multiplexers, by attempting to assign the first global conductor to a second one of the first multiplexers and a second one of the second multiplexers.

Claim 23

The method of claim 18 wherein at least one of the plurality of second signals is fed to a different global conductor if the procedure cannot assign the output of each first multiplexer to a global conductor.

Claim 24

A programmable logic circuit for producing a plurality of first signals, each of which is a programmable logic function of a plurality of second signals, the programmable logic circuit comprising: a plurality of logical arrays, each logical array having a plurality of inputs and at least one output with each output carrying a respective one of the plurality of first signals; a plurality of global conductors, each global conductor being fed by a respective one of the plurality of second signals; a plurality of first multiplexers, each of which has a plurality of inputs with each input being connected to a respective one of the global conductors, and an output; and a plurality of second multiplexers, each of which has a plurality of inputs with each input being connected to the output of a uniquely respective one of the first multiplexers, and an output connected to the input of a respective one of the logic array blocks, wherein each of the global conductors has two unique paths through two different first multiplexers to a single logic array block and each global conductor also has two unique paths from each one of the first multiplexers through two different second multiplexers to two different logic array blocks.

Claim 25

A programmable logic circuit for producing a plurality of first signals, each of which is a programmable logic function of a plurality of second signals, the programmable logic circuit comprising: a plurality of logical arrays, each logical array having a plurality of inputs and at least one output with each output carrying a respective one of the plurality of first signals; a plurality of global conductors, each global conductor being fed by a respective one of the plurality of second signals; a plurality of first multiplexers, each of which has a plurality of inputs with each input being connected to a respective one of the global conductors, and an output; and a plurality of second multiplexers, each of which has a plurality of inputs with each input being connected to the output of a uniquely respective one of the first multiplexers, and an output connected to the input of a respective one of the logic array blocks, wherein each of the global conductors has two unique paths through two different first multiplexers to a single logic array block and each global conductor also has two unique paths from each one of the first multiplexers through two different second multiplexers to two different logic array blocks.

Claim 26

The programmable logic circuit of claim 20 wherein the logical arrays further comprise logic members and spare logic members, the logical arrays having means for replacing defective logic members with spare logic members.

Claim 27

The programmable logic circuit of claim 20 wherein the logical arrays further comprise a plurality of word lines and a plurality of spare word lines, the logical arrays having means for replacing defective word lines with spare word lines.

Claim 28

The programmable logic circuit of claim 20 further comprising input and output pads controlled by tri-state buffers having means for programmatically controlling output voltage slew rate.

Claim 29

The programmable logic circuit of claim 20 further comprising a plurality of logical elements wherein the logical state of each logical element can be set to a desired state by connecting the logical elements in a serial arrangement having a first element whose state can be controlled and by passing a logical state string sequentially into the first element and through the serial arrangement until the desired state is obtained in each logical element.

Claim 30

The programmable logic circuit of claim 20 further comprising a plurality of logical elements wherein the logical state of each logical element can be monitored by connecting the logical elements in a serial arrangement having a last element whose state can be monitored such that the logical states of the logical elements form a logical state string, sequentially passing the logical state string through the serial arrangement, and monitoring the logical state of the last element in the serial arrangement.

Claim 31

The programmable logic circuit of claim 20 wherein each global conductor carries a signal and each one of the plurality of first multiplexers can be programmed to select one of the signals on the global conductors connected to its inputs to be transferred to its output.

Claim 32

The programmable logic circuit of claim 26 wherein each output of the plurality of logical arrays is connected to a respective one of the global conductors, the connections from logical array outputs to global conductors form a specific pattern, and the outputs of each logical array are partitioned into at least one group.

Claim 33

The programmable logic circuit of claim 27 wherein, in the specific pattern, the universe of first multiplexers fed by any one global conductor differs from the universe of first multiplexers fed by any other global conductor.

Claim 34

The programmable logic circuit of claim 27 wherein, in the specific pattern, any two inputs of any first multiplexer are connected to global conductors in different groups.

Claim 35

The programmable logic circuit of claim 27 wherein, in the specific pattern, the global conductors in any two groups form different logical arrays together with the first multiplexers to whose inputs they are connected form an acyclic chain.

Claim 36

The programmable logic circuit of claim 27 wherein the signals on the global conductors connected to the inputs of the plurality of first multiplexers are selected for transfer to the outputs of the second multiplexers by successively attempting to assign each global conductor to an output of one of the first multiplexers to which the global conductor is connected in accordance with the specific pattern until all multiplexer outputs are assigned, or until all possible attempts have been attempted.

Claim 37

The programmable logic circuit of claim 31 wherein each successive attempt attempts to assign each global conductor to an output of one of the second multiplexers to which the global conductor is essentially connected in the specific pattern using a procedure which operates recursively by: switching a first one of the first multiplexers to propagate signals from a first global conductor to the output of a first one of the second multiplexers if the first one of the first multiplexers has not been switched to propagate signals from any other global conductor to the output of the first one of the second multiplexers; or if a second global conductor has already been assigned to the output of the first one of the first multiplexers, by attempting to assign the first global conductor to a second one of the first multiplexers and a second one of the second multiplexers; or if the first one of the second multiplexers has already been assigned to the output of one of the first multiplexers, by attempting to assign the first global conductor to a second one of the first multiplexers and a second one of the second multiplexers.