US5668409A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit with edge connections and method
Assignee: Intersil Americas LLC
•
Filing: 1995-06-05
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Granted: 1997-09-16
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Expires: 2015-06-05
Abstract
Abstract A surface mountable integrated circuit is disclosed. Dies 1041 with edge connections 1080 are coupled to each other with the edge connection and to a printed circuit board 1070.
Inventors
- 👤 Stephen Joseph Gaul
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:46
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; H10W72/01; H10W72/019; H10W72/20; H10W90/00; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W72/071; H10W72/072; H10W72/07251; H10W72/07254; H10W72/241; H10W72/244; H10W72/251; H10W72/29; H10W72/941; H10W72/942; H10W72/944; H10W90/701; H10W90/721; H10W90/722; H10W90/724
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
138 words
An integrated circuit die with edge connectors comprising: a die of semiconductor material with first and second surfaces, an integrated circuit formed in the first surface, said die having an edge region with one or more edge surfaces disposed transverse to the first and second surfaces of the die, said edge region enclosing said integrated circuit; a plurality of edge leads, each edge lead comprising a conductive material, each edge lead having a controlled length extending in a first direction from the edge region toward the integrated circuit and having a controlled depth extending in a second direction along an edge surface and transverse to the first direction; a dielectric layer disposed between each lead and the semiconductor material of the die; a conductive layer connecting the integrated circuit to the leads on the edge of the die.
Claim 2
Dependent Claim
138 words
An integrated circuit die with edge connectors comprising: a die of semiconductor material with first and second surfaces, an integrated circuit formed in the first surface, said die having an edge region with one or more edge surfaces disposed transverse to the first and second surfaces of the die, said edge region enclosing said integrated circuit; a plurality of edge leads, each edge lead comprising a conductive material, each edge lead having a controlled length extending in a first direction from the edge region toward the integrated circuit and having a controlled depth extending in a second direction along an edge surface and transverse to the first direction; a dielectric layer disposed between each lead and the semiconductor material of the die; a conductive layer connecting the integrated circuit to the leads on the edge of the die.
Claim 3
Dependent Claim
17 words
The integrated circuit of claim 1 wherein the edge leads are coated with a reflowable solder material.
Claim 4
Dependent Claim
15 words
The integrated circuit of claim 1 wherein the conductive material of the leads is polysilicon.
Claim 5
Dependent Claim
11 words
The integrated circuit of claim 3 wherein the polysilicon is silicided.
Claim 6
Dependent Claim
15 words
The integrated circuit of claim 1 wherein the conductive material of the leads is metal.
Claim 7
Dependent Claim
24 words
The integrated circuit of claim 1 wherein the conductive material is a material selected from the group consisting of tungsten, copper, and titanium nitride.
Claim 8
Dependent Claim
12 words
The integrated circuit of claim 1 wherein the dielectric is silicon dioxide.
Claim 9
Independent Claim
211 words
A system for interconnecting two or more dies containing integrated circuits, each integrated circuit comprising: a die of semiconductor material with first and second surfaces, an integrated circuit formed in the first surface, said die having an edge region with one or more edge surfaces disposed transverse to the first and second surfaces of the die, said edge region enclosing said integrated circuit; a plurality of edge leads spaced apart from each other a controlled distance, each edge lead comprising a conductive material, each edge lead having a controlled length extending in a first direction from the edge region toward the integrated circuit and having a controlled depth extending in a second direction along an edge surface and transverse to the first direction; a dielectric layer disposed between each lead and the semiconductor material of the die; a conductive layer connecting the integrated circuit to the leads on the edge of the die; and a printed circuit board having a planar surface comprising a plurality of circuit traces, said circuit traces being spaced apart from each other by a distance corresponding to the the distance between adjacent edge leads of said dies; wherein said dies are coupled by their respective edge leads to the circuit traces on the printed circuit board.
Claim 10
Independent Claim
211 words
A system for interconnecting two or more dies containing integrated circuits, each integrated circuit comprising: a die of semiconductor material with first and second surfaces, an integrated circuit formed in the first surface, said die having an edge region with one or more edge surfaces disposed transverse to the first and second surfaces of the die, said edge region enclosing said integrated circuit; a plurality of edge leads spaced apart from each other a controlled distance, each edge lead comprising a conductive material, each edge lead having a controlled length extending in a first direction from the edge region toward the integrated circuit and having a controlled depth extending in a second direction along an edge surface and transverse to the first direction; a dielectric layer disposed between each lead and the semiconductor material of the die; a conductive layer connecting the integrated circuit to the leads on the edge of the die; and a printed circuit board having a planar surface comprising a plurality of circuit traces, said circuit traces being spaced apart from each other by a distance corresponding to the the distance between adjacent edge leads of said dies; wherein said dies are coupled by their respective edge leads to the circuit traces on the printed circuit board.
Claim 11
Dependent Claim
20 words
The system of claim 8 wherein the dies are generally transverse to the planar surface of the printed circuit board.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-15 | 2001-03-17 | 2001-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-15 | 2005-03-17 | 2005-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-15 | 2009-03-17 | 2009-09-16 | $7700.00 | Window Closed / Lapsed |