Patent US3224807A successfully refreshed from Google Patents.
US5362986A
Expired / Lapsed
US
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Vertical chip mount memory package with packaging substrate and memory chip pairs
Assignee: International Business Machines Corp
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Filing: 1993-08-19
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Granted: 1994-11-08
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Expires: 2013-08-19
Abstract
Abstract A packaging substrate (10) is populated with memory chip cube(s) (40) and horizontally mounted interconnect chip(s) (19)mounted on the substrate which are joined during assembly using two kinds of lead tin solder alloys to form the memory chip cube. One is a high melting point lead tin alloy (HMA), another is a lower melting point lead tin alloy (LMA). The memory chip pairs (11) of the memory cube are formed by placing functional memory chips over other functional memory chips before they were diced. The chip pads of the individual memory chips and the lead tin pads of the memory chips within the wafer are aligned and the high melting point lead tin solder is reflowed, forming memory chip pairs.
Inventors
- 👤 John M. Angiulli
- 👤 Eugene S. Kolankowsky
- 👤 Richard R. Konian
- 👤 Leon L. Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 14:59
CPC Classifications
H; H10; H10W; H10W90/00; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49144
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
220 words
An integrated circuit chip package comprising: a packaging wiring base substrate having a planar surface and having a plurality of bonding interconnect pads located on said planar surface, at least one interconnection chip horizontally mounted on said planar surface and disposed horizontally and parallel to the planar surface with interconnection to first selected ones of said plurality of bonding interconnect pads, a plurality of integrated circuit memory chips arranged as memory chip pairs mounted on the planar surface of the base substrate and electrically connected and mechanically bonded to second selected ones of said plurality of bonding interconnect pads located on said planar surface, said memory chip pairs being placed vertically and normal to the planar surface of said base substrate in close spacing between one another to form a memory chip cube mounted on said second selected ones of said plurality of bonding interconnect pads located on said planar surface of the packaging wiring base substrate, a plurality of interconnections between said first and second selected ones of said plurality of interconnect pads located to interconnect said at least one interconnection chip and said memory chip pairs, and an enclosure for said at least one interconnection chip and said plurality of integrated circuit memory chips to cover the integrated circuit memory chips which are mounted on said base substrate.
Claim 2
Dependent Claim
220 words
An integrated circuit chip package comprising: a packaging wiring base substrate having a planar surface and having a plurality of bonding interconnect pads located on said planar surface, at least one interconnection chip horizontally mounted on said planar surface and disposed horizontally and parallel to the planar surface with interconnection to first selected ones of said plurality of bonding interconnect pads, a plurality of integrated circuit memory chips arranged as memory chip pairs mounted on the planar surface of the base substrate and electrically connected and mechanically bonded to second selected ones of said plurality of bonding interconnect pads located on said planar surface, said memory chip pairs being placed vertically and normal to the planar surface of said base substrate in close spacing between one another to form a memory chip cube mounted on said second selected ones of said plurality of bonding interconnect pads located on said planar surface of the packaging wiring base substrate, a plurality of interconnections between said first and second selected ones of said plurality of interconnect pads located to interconnect said at least one interconnection chip and said memory chip pairs, and an enclosure for said at least one interconnection chip and said plurality of integrated circuit memory chips to cover the integrated circuit memory chips which are mounted on said base substrate.
Claim 3
Dependent Claim
34 words
The package of claim 1 wherein said at least one interconnection chip and the memory chip pairs of the memory chip cube are connected electrically to the packaging wiring base substrate with solder balls.
Claim 4
Dependent Claim
45 words
The package of claim 1 wherein said at least one interconnection chips and the memory chips are wired together and are wired to a next level package through wiring inside the packaging wiring base substrate and an input/output line of the integrated circuit chip package.
Claim 5
Dependent Claim
31 words
The package of claim 1 wherein a memory chip pair of said plurality of integrated circuit memory chips is formed by a pair of memory chips joined together with solder balls.
Claim 6
Dependent Claim
107 words
The package of claim 1 wherein a pair of memory chips form a memory chip pair joined together with two rows of solder balls on opposite edges of the memory chip pair, a first row of said solder balls being located on a bottom edge of a chip pair serving to connect the chip pair mechanically to each other and to connect signal and power I/O of the memory chips to power and I/O signal wiring of the packaging base substrate, and wherein a second row of said solder balls is positioned on a top edge of said chip pair for maintaining spacing of the chip pairs.
Claim 7
Dependent Claim
54 words
The package of claim 5 wherein, during assembly of each memory chip cube, the second row of said solder balls maintains the spacing of the chip pairs and connects a temporary silicon assembly bar to the chip pairs to maintain the spacing when the memory chip pairs are assembled into a memory chip cube.
Claim 8
Dependent Claim
60 words
The package of claim 5 wherein pads for solder connection to an edge of a chip pair are of even number in a row and the pads have mirror symmetry such that, when said memory chips are turned face to face to form said chip pairs, the pads for solder connection to the edge of a chip pair are aligned.
Claim 9
Dependent Claim
55 words
The package of claim 1 wherein a plurality of the memory chip pairs are joined together to form a memory cube and joined to the packaging wiring base substrate so that individual solder balls on the packaging wiring base substrate are connected to one signal or power I/O of either chip in the chip pair.
Claim 10
Dependent Claim
32 words
The package of claim 1 wherein the packaging wiring base substrate comprises a silicon substrate to which a cold plate is directly attached for cooling the back side of the silicon substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-07 | 1998-05-09 | 1998-11-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-07 | 2002-05-09 | 2002-11-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-07 | 2006-05-09 | 2006-11-08 | $7700.00 | Window Closed / Lapsed |