Antifuse with double via, spacer-defined contact

Claim 2

An antifuse structure in an integrated circuit comprising a first metal interconnection layer on a first insulating layer; a relatively thin, second insulating layer over said first metal interconnection layer and said first insulating layer, said second insulating layer having a first aperture therethrough where the antifuse structure is to be located, said first aperture forming sides of said second insulating layer; a first spacer region in said first aperture on said sides of said second insulating layer; a programming layer on said second insulating layer and on said first spacer region contacting said first metal interconnection layer, said programming layer conformally following said first spacer region into said first aperture, and forming sides of said programming layer, said first spacer region comprising a material used for said programming layer; a second spacer region on said sides of said programming layer; a barrier metal layer on said programming layer and on said second spacer region contacting said programming layer; a relatively thick, third insulating layer on said barrier metal layer, said third insulating layer having a second aperture therethrough exposing a portion of said barrier metal layer; and a second metal interconnection layer on said third insulating layer contacting said portion of said barrier metal layer; whereby said first and second spacer regions force programming away from said sides of said second insulating layer permitting a relatively consistent programming voltage for the antifuse structure and a relatively uniform conducting link between said first and second metal interconnection layers.

Claim 3

The antifuse structure of claim 1 wherein said material used for said first spacer region and said programming layer comprises amorphous silicon.

Claim 4

The antifuse structure of claim 1 wherein said second spacer region comprises silicon dioxide.

Claim 5

The antifuse structure of claim 1 wherein said second spacer region comprises silicon nitride.

Claim 6

The antifuse structure of claim 1 wherein said second spacer region comprises a material used for said programming layer.

Claim 7

The antifuse structure of claim 1 wherein said second insulating layer has a thickness from 2500 to 3000 Å.

Claim 8

The antifuse structure of claim 1 wherein said third insulating layer has a thickness from 5000 to 12000 Å.

Claim 9

The antifuse structure of claim 1 wherein said first metal interconnection layer comprises a barrier metal layer on an aluminum alloy layer.

Claim 10

An antifuse structure in an integrated circuit comprising: a first metal interconnection layer on a first insulating layer; a relatively thin, second insulating layer over said first metal interconnection layer and the first insulating layer, said second insulating layer having a first aperture therethrough exposing said first metal interconnection layer and said second insulating layer having sides that are sloped; a programming layer on said second insulating layer contacting said first metal interconnection layer, said programming layer conformally following said second insulating layer into said first aperture and forming sides of said programming layer; a spacer region on said sides of said programming layer; a barrier metal layer on said programming layer and on said spacer region contacting said programming layer; a relatively thick, third insulating layer on said barrier metal layer, said third insulating layer having a second aperture therethrough exposing a porion of said barrier metal layer; and a second metal interconnection layer on said third insulating layer contacting said portion of said barrier metal layer.

Claim 11

An antifuse structure in an integrated circuit comprising: a first metal interconnection layer on a first insulating layer; a relatively thin, second insulating layer over said first metal interconnection layer and the first insulating layer, said second insulating layer having a first aperture therethrough exposing said first metal interconnection layer and said second insulating layer having sides that are sloped; a programming layer on said second insulating layer contacting said first metal interconnection layer, said programming layer conformally following said second insulating layer into said first aperture and forming sides of said programming layer; a spacer region on said sides of said programming layer; a barrier metal layer on said programming layer and on said spacer region contacting said programming layer; a relatively thick, third insulating layer on said barrier metal layer, said third insulating layer having a second aperture therethrough exposing a porion of said barrier metal layer; and a second metal interconnection layer on said third insulating layer contacting said portion of said barrier metal layer.

Claim 12

The antifuse structure of claim 9 wherein said second insulating layer comprises boron and phosphorus doped silicon glass.

Claim 13

The antifuse structure of claim 9 wherein said second insulating layer has a thickness from 2500 to 3000 Å.

Claim 14

The antifuse structure of claim 9 wherein said third insulating layer has a thickness from 5000 to 12000 Å.

Claim 15

The antifuse structure of claim 9 wherein said first metal interconnection layer comprises an aluminum alloy and a barrier metal layer.

Claim 16

An antifuse structure in an integrated circuit including a first insulating layer on a substrate comprising: a first metal interconnection layer on the first insulating layer; a spacer region over said substrate and adjacent to said first metal interconnection layer and the first insulating layer; a relatively thin, second insulating layer over said first metal interconnection layer and over said spacer region, said second insulating layer having a first aperture therethrough exposing said first metal interconnection layer, said first aperture forming sides of said second insulating layer; a second spacer region in said first aperture on said sides of said second insulating layer; a programming layer on said second insulating layer contacting said first metal interconnection layer; a barrier metal layer on said programming layer contacting said programming layer; forming a relatively thick, third insulating layer on said barrier metal layer, said third insulating layer having a second aperture there through exposing a porion of said barrier metal layer; and a second metal interconnection layer on said third insulating layer contacting said portion of said barrier metal layer.

Claim 17

An antifuse structure in an integrated circuit including a first insulating layer on a substrate comprising: a first metal interconnection layer on the first insulating layer; a spacer region over said substrate and adjacent to said first metal interconnection layer and the first insulating layer; a relatively thin, second insulating layer over said first metal interconnection layer and over said spacer region, said second insulating layer having a first aperture therethrough exposing said first metal interconnection layer, said first aperture forming sides of said second insulating layer; a second spacer region in said first aperture on said sides of said second insulating layer; a programming layer on said second insulating layer contacting said first metal interconnection layer; a barrier metal layer on said programming layer contacting said programming layer; forming a relatively thick, third insulating layer on said barrier metal layer, said third insulating layer having a second aperture there through exposing a porion of said barrier metal layer; and a second metal interconnection layer on said third insulating layer contacting said portion of said barrier metal layer.

Claim 18

The antifuse structure of claim 14 wherein said spacer region comprises a phosphorus doped silicon glass.

Claim 19

The antifuse structure of claim 14 wherein said spacer region comprises a material used for forming said second insulating layer.

Claim 20

An antifuse structure in an integrated circuit including a first insulating layer on a substrate comprising: a first metal interconnection layer on the first insulating layer; a spacer region over said substrate and adjacent to said first metal interconnection layer and the first insulating layer, said spacer region comprising a phosphorous doped silicon glass; a relatively thin, second insulating layer over said first metal interconnection layer and said spacer region, said second insulating layer having a first aperture therethrough exposing said first metal interconnection layer, said first aperture forming sides of said second insulating layer; a second spacer region in said first aperture on said sides of said second insulating layer; a programming layer on said second insulating layer and on said second spacer region contacting said first metal interconnection layer, said programming layer conformally following said first spacer region into said first aperture, and forming sides of said programming layer; a third spacer region on said sides of said programming layer; a barrier metal layer on said programming layer and on the third spacer region contacting said programming layer; forming a relatively thick, third insulating layer on said barrier metal layer, said third insulating layer having a second aperture there through exposing a porion of said barrier metal layer; and a second metal interconnection layer on said third insulating layer contacting said portion of said barrier metal layer.

Claim 21

An antifuse structure in an integrated circuit including a first insulating layer on a substrate comprising: a first metal interconnection layer on the first insulating layer; a spacer region over said substrate and adjacent to said first metal interconnection layer and the first insulating layer, said spacer region comprising a phosphorous doped silicon glass; a relatively thin, second insulating layer over said first metal interconnection layer and said spacer region, said second insulating layer having a first aperture therethrough exposing said first metal interconnection layer, said first aperture forming sides of said second insulating layer; a second spacer region in said first aperture on said sides of said second insulating layer; a programming layer on said second insulating layer and on said second spacer region contacting said first metal interconnection layer, said programming layer conformally following said first spacer region into said first aperture, and forming sides of said programming layer; a third spacer region on said sides of said programming layer; a barrier metal layer on said programming layer and on the third spacer region contacting said programming layer; forming a relatively thick, third insulating layer on said barrier metal layer, said third insulating layer having a second aperture there through exposing a porion of said barrier metal layer; and a second metal interconnection layer on said third insulating layer contacting said portion of said barrier metal layer.

Claim 22

An antifuse structure in an integrated circuit comprising a first metal interconnection layer on a first insulating layer; a relatively thin, second insulating layer over said first metal interconnection layer and said first insulating layer, said second insulating layer having a first aperture therethrough where the antifuse structure is to be located, said first aperture forming sides of said second insulating layer; a first spacer region in said first aperture on said sides of said second insulating layer; a programming layer on said second insulating layer and on said first spacer region contacting said first metal interconnection layer, said programming layer conformally following said first spacer region into said first aperture, and forming sides of said programming layer; a second spacer region on said sides of said programming layer said second spacer region comprising a material used for said programming layer; a barrier metal layer on said programming layer and on said second spacer region contacting said programming layer; a relatively thick, third insulating layer on said barrier metal layer, said third insulating layer having a second aperture therethrough exposing a portion of said barrier metal layer; and a second metal interconnection layer on said third insulating layer contacting said portion of said barrier metal layer; whereby said first and second spacer regions force programming away from said sides of said second, insulating layer permitting a relatively consistent programming voltage for the antifuse structure and a relatively uniform conducting link between said first and second metal interconnection layers.

Claim 23

An antifuse structure in an integrated circuit comprising a first metal interconnection layer on a first insulating layer; a relatively thin, second insulating layer over said first metal interconnection layer and said first insulating layer, said second insulating layer having a first aperture therethrough where the antifuse structure is to be located, said first aperture forming sides of said second insulating layer; a first spacer region in said first aperture on said sides of said second insulating layer; a programming layer on said second insulating layer and on said first spacer region contacting said first metal interconnection layer, said programming layer conformally following said first spacer region into said first aperture, and forming sides of said programming layer; a second spacer region on said sides of said programming layer said second spacer region comprising a material used for said programming layer; a barrier metal layer on said programming layer and on said second spacer region contacting said programming layer; a relatively thick, third insulating layer on said barrier metal layer, said third insulating layer having a second aperture therethrough exposing a portion of said barrier metal layer; and a second metal interconnection layer on said third insulating layer contacting said portion of said barrier metal layer; whereby said first and second spacer regions force programming away from said sides of said second, insulating layer permitting a relatively consistent programming voltage for the antifuse structure and a relatively uniform conducting link between said first and second metal interconnection layers.

Claim 24

The antifuse structure of claim 18 wherein said first spacer region comprises a material used for said programming layer.

Claim 25

The antifuse structure of claim 18 wherein said material used for said second spacer region and said programming layer comprises amorphous silicon.

Claim 26

The antifuse structure of claim 18 wherein said first spacer region comprises silicon dioxide.

Claim 27

The antifuse structure of claim 18 wherein said first spacer region comprises silicon nitride.

Claim 28

The antifuse structure of claim 18 wherein said second insulating layer had a thickness from 2500 to 3000 Å.

Claim 29

The method of claim 18 wherein said third insulating layer has a thickness from 5000 to 12000 Å.

Claim 30

The method of claim 18 wherein said first metal interconnection layer comprises a barrier metal layer on an aluminum alloy layer.

Claim 31

The antifuse structure of claim 9 wherein the spacer region comprises a material used for said programming layer.

Claim 32

The antifuse structure of claim 9 wherein the spacer region comprises amorphous silicon.

Claim 33

An antifuse structure in an integrated circuit comprising: a first metal interconnection layer on a first insulating layer; a relatively thin, second insulating layer over said first metal interconnection layer and the first insulating layer, said second insulating layer having a first aperture therethrough exposing said first metal interconnection layer and said second insulating layer having sides that are sloped; a programming layer on said second insulating layer contacting said first metal interconnection layer, said programming layer having sides; a spacer region on said sides of said programming layer; a barrier metal layer on said programming layer and on said spacer region contacting said programming layer; a relatively thick, third insulating layer on said barrier metal layer, said third insulating layer having a second aperture therethrough exposing a porion of said barrier metal layer, said third insulating layer having a thickness from 5000 to 12000 Å; and a second metal interconnection layer on said third insulating layer contacting said portion of said barrier metal layer.

Claim 34

An antifuse structure in an integrated circuit comprising: a first metal interconnection layer on a first insulating layer; a relatively thin, second insulating layer over said first metal interconnection layer and the first insulating layer, said second insulating layer having a first aperture therethrough exposing said first metal interconnection layer and said second insulating layer having sides that are sloped; a programming layer on said second insulating layer contacting said first metal interconnection layer, said programming layer having sides; a spacer region on said sides of said programming layer; a barrier metal layer on said programming layer and on said spacer region contacting said programming layer; a relatively thick, third insulating layer on said barrier metal layer, said third insulating layer having a second aperture therethrough exposing a porion of said barrier metal layer, said third insulating layer having a thickness from 5000 to 12000 Å; and a second metal interconnection layer on said third insulating layer contacting said portion of said barrier metal layer.

Claim 35

The antifuse structure of claim 28 wherein said second insulating layer comprises boron and phosphorous doped silicon glass.

Claim 36

The antifuse structure of claim 28 wherein said second insulating layer has a thickness from 2500 to 3000 Å.

Claim 37

The antifuse structure of claim 28 wherein said first metal interconnection layer comprises an aluminum alloy and a barrier metal layer.

Claim 38

The antifuse structure of claim 28 wherein the spacer region comprises a material used for said programming layer.

Claim 39

The antifuse structure of claim 28 wherein the spacer region comprises amorphous silicon.

Claim 40

The antifuse structure of claim 14 wherein the second spacer region comprises amorphous silicon.

Claim 41

The antifuse structure of claim 17 wherein the second spacer region comprises a material used for said programming layer.

Claim 42

The antifuse structure of claim 17 wherein the second spacer region comprises amorphous silicon.

Claim 43

The antifuse structure of claim 17 wherein the third spacer region comprises a material used for said programming layer.

Claim 44

The antifuse structure of claim 17 wherein the third spacer region comprises amorphous silicon.