US5387812A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrically programmable antifuse having a metal to metal structure
Assignee: Microsemi SoC Corp
•
Filing: 1992-09-18
•
Granted: 1995-02-07
•
Expires: 2012-09-18
Abstract
Abstract A metal-to metal antifuse device is provided in a double layer metal interconnect structure. A lower electrode comprises a first multilayer metal layer interconnect disposed on an insulator. An inter-metal dielectric is disposed on the first metal layer interconnect having an antifuse via. An antifuse material layer is disposed in the antifuse via and having an upper electrode comprising a second multilayer metal layer interconnect.
Inventors
- 👤 Abdul R. Forouhi
- 👤 Esmat Z. Hamdy
- 👤 Chenming Hu
- 👤 John L. McCollum
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:41
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491; H10W20/41; H10W20/425
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
117 words
An antifuse structure in an integrated circuit comprising: a substrate having an insulating layer disposed on an upper surface thereof: a lower electrode comprising a first multilayer metal interconnect layer in said integrated circuit, said first multilayer metal interconnect layer disposed on said insulating layer; an inter-metal dielectric layer disposed on said lower electrode, said inter-metal dielectric layer including an antifuse via formed therethrough communicating with said first multilayer metal interconnect layer; an antifuse material layer disposed in said antifuse via, said antifuse material layer comprising a layer of silicon nitride; and an upper antifuse electrode disposed on said antifuse material layer, said upper antifuse electrode comprising a second multilayer metal interconnect layer in said integrated circuit.
Claim 2
Dependent Claim
117 words
An antifuse structure in an integrated circuit comprising: a substrate having an insulating layer disposed on an upper surface thereof: a lower electrode comprising a first multilayer metal interconnect layer in said integrated circuit, said first multilayer metal interconnect layer disposed on said insulating layer; an inter-metal dielectric layer disposed on said lower electrode, said inter-metal dielectric layer including an antifuse via formed therethrough communicating with said first multilayer metal interconnect layer; an antifuse material layer disposed in said antifuse via, said antifuse material layer comprising a layer of silicon nitride; and an upper antifuse electrode disposed on said antifuse material layer, said upper antifuse electrode comprising a second multilayer metal interconnect layer in said integrated circuit.
Claim 3
Dependent Claim
115 words
An antifuse structure in an integrated circuit comprising: a substrate having an insulating layer disposed on an upper surface thereof; a lower electrode comprising a first multilayer metal interconnect layer in said integrated circuit, said first multilayer metal interconnect layer disposed on said insulating layer; an antifuse material layer disposed on said lower electrode, said antifuse material layer comprising a layer of silicon nitride; an inter-metal dielectric layer disposed on said antifuse material layer, said inter-metal dielectric layer including an antifuse via formed therethrough communicating with said antifuse material; and an upper antifuse electrode disposed on said antifuse material layer, said upper antifuse electrode comprising a second multilayer metal interconnect layer in said integrated circuit.
Claim 4
Dependent Claim
115 words
An antifuse structure in an integrated circuit comprising: a substrate having an insulating layer disposed on an upper surface thereof; a lower electrode comprising a first multilayer metal interconnect layer in said integrated circuit, said first multilayer metal interconnect layer disposed on said insulating layer; an antifuse material layer disposed on said lower electrode, said antifuse material layer comprising a layer of silicon nitride; an inter-metal dielectric layer disposed on said antifuse material layer, said inter-metal dielectric layer including an antifuse via formed therethrough communicating with said antifuse material; and an upper antifuse electrode disposed on said antifuse material layer, said upper antifuse electrode comprising a second multilayer metal interconnect layer in said integrated circuit.
References Cited (Backward Citations)
US3634929A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-06 | 1998-08-08 | 1999-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-06 | 2002-08-08 | 2003-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-06 | 2006-08-08 | 2007-02-07 | $7700.00 | Window Closed / Lapsed |