US5657293A
Expired / Lapsed
US
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Integrated circuit memory with back end mode disable
Assignee: Round Rock Research LLC
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Filing: 1995-08-23
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Granted: 1997-08-12
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Expires: 2015-08-23
Abstract
Abstract A memory circuit is described which can operate in one of a number of operating modes. The operating mode of the memory circuit can be changed in a non-volatile manner after the memory circuit is packaged to reduce production scrap or meet market demands. Disable circuitry is described which includes an anti-fuse that can be externally selectively blown to disable an operating mode. Control circuitry included in the memory circuit enables a new operating mode after the first operating mode is disable. A method of selectively disabling an operating mode is described. A hierarchical scheme is also described for enabling a new operating mode from a group of operating modes, for example page-mode, extended data output (EDO), or burst EDO.
Inventors
- 👤 Todd Merritt
- 👤 Troy Manning
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:21
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/1045
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
80 words
An integrated circuit memory having a plurality of operating modes, the integrated circuit memory comprising: a plurality of addressable memory cells for storing data; a non-volatile disable circuit to selectively disable the first one of the plurality of operating modes; and control circuitry coupled to the non-volatile disable circuit for operating the integrated memory circuit in one of the plurality of operating modes in response to the non-volatile disable circuit, wherein the non-volatile disable circuit comprises a selectively blowable fuse.
Claim 2
Dependent Claim
80 words
An integrated circuit memory having a plurality of operating modes, the integrated circuit memory comprising: a plurality of addressable memory cells for storing data; a non-volatile disable circuit to selectively disable the first one of the plurality of operating modes; and control circuitry coupled to the non-volatile disable circuit for operating the integrated memory circuit in one of the plurality of operating modes in response to the non-volatile disable circuit, wherein the non-volatile disable circuit comprises a selectively blowable fuse.
Claim 3
Dependent Claim
123 words
An integrated circuit memory having a plurality of operating modes, the integrated circuit memory comprising: a plurality of addressable memory cells for storing data; a non-volatile disable circuit to selectively disable a first one of the plurality of operating modes; and control circuitry coupled to the non-volatile disable circuit for operating the integrated memory circuit in one of the plurality of operating modes in response to the non-volatile disable circuit, wherein the non-volatile disable circuit comprises: a latch circuit which produces an output that indicates when the first one of the plurality of operating modes is disabled; and a fuse circuit connected to the latch circuit which produces a pre-determined output used to permanently disable the first one of the plurality operating modes.
Claim 4
Dependent Claim
123 words
An integrated circuit memory having a plurality of operating modes, the integrated circuit memory comprising: a plurality of addressable memory cells for storing data; a non-volatile disable circuit to selectively disable a first one of the plurality of operating modes; and control circuitry coupled to the non-volatile disable circuit for operating the integrated memory circuit in one of the plurality of operating modes in response to the non-volatile disable circuit, wherein the non-volatile disable circuit comprises: a latch circuit which produces an output that indicates when the first one of the plurality of operating modes is disabled; and a fuse circuit connected to the latch circuit which produces a pre-determined output used to permanently disable the first one of the plurality operating modes.
Claim 5
Dependent Claim
16 words
The integrated circuit memory of claim 2 where the fuse circuit comprises a selectively blowable anti-fuse.
Claim 6
Dependent Claim
45 words
The integrated circuit memory of claim 2 where the fuse circuit comprises: a high voltage MOS transistor having its drain coupled to a low voltage line; and an anti-fuse electrically coupled between a variable voltage source and a source of the high voltage MOS transistor.
Claim 7
Dependent Claim
78 words
A memory package comprising: a packaged integrated memory circuit having a plurality of operating modes comprising; addressable memory cells for storing data; a non-volatile disable circuit to selectively disable the first one of the plurality of operating modes; and control circuitry coupled to the non-volatile disable circuit for operating the integrated memory circuit in one of the plurality of operating modes in response to the non-volatile disable circuit, wherein the non-volatile disable circuit comprises a selectively blowable fuse.
Claim 8
Dependent Claim
78 words
A memory package comprising: a packaged integrated memory circuit having a plurality of operating modes comprising; addressable memory cells for storing data; a non-volatile disable circuit to selectively disable the first one of the plurality of operating modes; and control circuitry coupled to the non-volatile disable circuit for operating the integrated memory circuit in one of the plurality of operating modes in response to the non-volatile disable circuit, wherein the non-volatile disable circuit comprises a selectively blowable fuse.
Claim 9
Dependent Claim
121 words
A memory package comprising: a packaged integrated memory circuit having a plurality of operating modes comprising; addressable memory cells for storing data; a non-volatile disable circuit to selectively disable a first one of the plurality of operating modes; and control circuitry coupled to the non-volatile disable circuit for operating the integrated memory circuit in one of the plurality of operating modes in response to the non-volatile disable circuit, wherein the non-volatile disable circuit comprises: a latch circuit which produces an output that indicates when the first one of the plurality of operating modes is disabled; and a fuse circuit connected to the latch circuit which produces a pre-determined output used to permanently disable the first one of the plurality operating modes.
Claim 10
Dependent Claim
121 words
A memory package comprising: a packaged integrated memory circuit having a plurality of operating modes comprising; addressable memory cells for storing data; a non-volatile disable circuit to selectively disable a first one of the plurality of operating modes; and control circuitry coupled to the non-volatile disable circuit for operating the integrated memory circuit in one of the plurality of operating modes in response to the non-volatile disable circuit, wherein the non-volatile disable circuit comprises: a latch circuit which produces an output that indicates when the first one of the plurality of operating modes is disabled; and a fuse circuit connected to the latch circuit which produces a pre-determined output used to permanently disable the first one of the plurality operating modes.
Claim 11
Dependent Claim
15 words
The memory package of claim 6 where the fuse circuit comprises a selectively blowable anti-fuse.
Claim 12
Dependent Claim
44 words
The memory package of claim 6 where the fuse circuit comprises: a high voltage MOS transistor having its drain coupled to a low voltage line; and an anti-fuse electrically coupled between a variable voltage source and a source of the high voltage MOS transistor.
Claim 13
Dependent Claim
148 words
A memory having a plurality of operating modes comprising a plurality of addressable memory cells for storing data, a non-volatile disable circuit to selectively disable a first one of the plurality of operating modes, and control circuitry coupled to the non-volatile disable circuit for operating the memory in one of the plurality of operating modes in response to the non-volatile disable circuit, the memory manufactured by the process comprising the steps of: fabricating an integrated circuit memory having a non-volatile disable circuit to selectively disable a first one of the plurality of operating modes, and control circuitry coupled to the non-volatile disable circuit for operating the memory in one of the plurality of operating modes in response to the non-volatile disable circuit; packaging the integrated circuit memory; and programming the non-volatile disable circuit by selectively activating a fuse circuit to disable one of the plurality of operating modes.
Claim 14
Dependent Claim
148 words
A memory having a plurality of operating modes comprising a plurality of addressable memory cells for storing data, a non-volatile disable circuit to selectively disable a first one of the plurality of operating modes, and control circuitry coupled to the non-volatile disable circuit for operating the memory in one of the plurality of operating modes in response to the non-volatile disable circuit, the memory manufactured by the process comprising the steps of: fabricating an integrated circuit memory having a non-volatile disable circuit to selectively disable a first one of the plurality of operating modes, and control circuitry coupled to the non-volatile disable circuit for operating the memory in one of the plurality of operating modes in response to the non-volatile disable circuit; packaging the integrated circuit memory; and programming the non-volatile disable circuit by selectively activating a fuse circuit to disable one of the plurality of operating modes.
Claim 15
Independent Claim
89 words
A method of changing an operating mode in an integrated memory circuit, comprising the steps in the order of: packaging an integrated memory circuit including control circuitry for operating the integrated memory circuit in a first mode from a plurality of modes, and a non-volatile disable circuit coupled to the control circuitry to selectively disable the first mode; programming the non-volatile disable circuit; testing the packaged integrated memory circuit; disabling the first mode using the programmed non-volatile disable circuit. and enabling a second mode from the plurality of modes.
Claim 16
Independent Claim
89 words
A method of changing an operating mode in an integrated memory circuit, comprising the steps in the order of: packaging an integrated memory circuit including control circuitry for operating the integrated memory circuit in a first mode from a plurality of modes, and a non-volatile disable circuit coupled to the control circuitry to selectively disable the first mode; programming the non-volatile disable circuit; testing the packaged integrated memory circuit; disabling the first mode using the programmed non-volatile disable circuit. and enabling a second mode from the plurality of modes.
Claim 17
Dependent Claim
37 words
The method of claim 10 wherein the step of programming the non-volatile disable circuit further comprises the sub-step of: selectively blowing a fuse circuit to produce a pre-determined output used to permanently disable the first operating mode.
Claim 18
Dependent Claim
12 words
The method of claim 10 wherein the fuse circuit comprises an anti-fuse.
Claim 19
Dependent Claim
25 words
The method of claim 10 wherein the first mode is an extended data output (EDO) mode, and the second mode is a page mode operation.
Claim 20
Dependent Claim
28 words
The method of claim 10 wherein the first mode is an extended data output (EDO) mode, and the second mode is a burst extended data output (BEDO) mode.
Claim 21
Dependent Claim
28 words
The method of claim 10 wherein the first mode is a burst extended data output (BEDO) mode, and the second mode is a extended data output (EDO) mode.
Claim 22
Dependent Claim
81 words
An integrated circuit in memory having a plurality of operating modes, the integrated circuit memory comprising: a plurality of addressable memory cells for storing data; a non-volatile disable circuit to selectively disable a first one of the plurality of operating modes; and control circuitry coupled to the non-volatile disable circuit for operating the integrated memory circuit in one of the plurality of operating modes in response to the non-volatile disable circuit, wherein the non-volatile disable circuit comprises a selectively blowable anti-fuse.
Claim 23
Dependent Claim
81 words
An integrated circuit in memory having a plurality of operating modes, the integrated circuit memory comprising: a plurality of addressable memory cells for storing data; a non-volatile disable circuit to selectively disable a first one of the plurality of operating modes; and control circuitry coupled to the non-volatile disable circuit for operating the integrated memory circuit in one of the plurality of operating modes in response to the non-volatile disable circuit, wherein the non-volatile disable circuit comprises a selectively blowable anti-fuse.
Claim 24
Dependent Claim
78 words
A memory package comprising: a packaged integrated memory circuit having a plurality of operating modes comprising; addressable memory cells for storing data; a non-volatile disable circuit to selectively disable a first one of the plurality of operating modes; and control circuitry coupled to the non-volatile disable circuit for operating the integrated memory circuit in one of the plurality of operating modes in response to the non-volatile disable circuit, wherein the non-volatile disable circuit comprises a selectively blowable anti-fuse.
Claim 25
Dependent Claim
78 words
A memory package comprising: a packaged integrated memory circuit having a plurality of operating modes comprising; addressable memory cells for storing data; a non-volatile disable circuit to selectively disable a first one of the plurality of operating modes; and control circuitry coupled to the non-volatile disable circuit for operating the integrated memory circuit in one of the plurality of operating modes in response to the non-volatile disable circuit, wherein the non-volatile disable circuit comprises a selectively blowable anti-fuse.
References Cited (Backward Citations)
US4609985A
Cited
US4876671A
Cited
US4833650A
Cited
US4990800A
Cited
US4996672A
Cited
US5159676A
Cited
US5408435A
Cited
US5245577A
Cited
EP0513968A2
Cited
US5241496A
Cited
US5331196A
Cited
US5324681A
Cited
US5110754A
Cited
US5233206A
Cited
US5200652A
Cited
US5410507A
Cited
US5257222A
Cited
US5208177A
Cited
US5148391A
Cited
US5257225A
Cited
US5388248A
Cited
US5250459A
Cited
US5305267A
Cited
US5282158A
Cited
US5301159A
Cited
US5331593A
Cited
US5315177A
Cited
US5349566A
Cited
US5335202A
Cited
US5379250A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-11 | 2001-02-10 | 2001-08-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-11 | 2005-02-10 | 2005-08-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-11 | 2009-02-10 | 2009-08-12 | $7700.00 | Window Closed / Lapsed |