US4609985A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microcomputer with severable ROM
Assignee: STMicroelectronics lnc USA
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Filing: 1982-12-30
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Granted: 1986-09-02
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Expires: 2002-12-30
Abstract
Abstract A microcomputer has provision for both on-chip ROM (on the same chip as the CPU) and off-chip ROM and which may operate with only on-chip ROM as only off-chip ROM has the hardware capability to disable on-chip ROM permanently, so that chips having defective ROM may be salvaged by being converted to computer chips that use only off-chip ROM.
Inventors
- 👤 Harold W. Dozier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:11
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/262; G06F9/268
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
239 words
A single-chip microcomputer comprising: a central processing unit (100) having at least two alternative memory access modes; input/output means (104) within said central processing unit (100) and connected to at least one external pin (102) thereof; and on-chip read-only memory (155) within said central processing unit (100); which microcomputer includes: disabling means (150), coupled to said pin (102) and responsive to application of a voltage in excess of 5 volts to said external pin (102) of said microcomputer and having a ROM disable output (152) connected to said on-chip read-only memory (155), to permanently disable said on-chip read-only memory (155), said disabling means including a resistance element (162) of limited current capacity, having first and second terminals, said second terminal being connected to ground and said first terminal being connected to a ROM-disable node (163), said node (163) being connected to a high-current capacity transistor (156) and to said ROM disable output (152), said node (163) being normally held at a predetermined first voltage state by connecting said node (163) to said second, grounded, terminal thereof, whereby said application of a voltage in excess of five volts results in said transistor (156) being gated open and causes said resistance element (162) to be destroyed and said ROM-disable node (163) to change to a second voltage; and means (170, 200), connected to said output (152) of said disabling means (150) and to a mode input (172), for accessing external memory.
Claim 2
Dependent Claim
239 words
A single-chip microcomputer comprising: a central processing unit (100) having at least two alternative memory access modes; input/output means (104) within said central processing unit (100) and connected to at least one external pin (102) thereof; and on-chip read-only memory (155) within said central processing unit (100); which microcomputer includes: disabling means (150), coupled to said pin (102) and responsive to application of a voltage in excess of 5 volts to said external pin (102) of said microcomputer and having a ROM disable output (152) connected to said on-chip read-only memory (155), to permanently disable said on-chip read-only memory (155), said disabling means including a resistance element (162) of limited current capacity, having first and second terminals, said second terminal being connected to ground and said first terminal being connected to a ROM-disable node (163), said node (163) being connected to a high-current capacity transistor (156) and to said ROM disable output (152), said node (163) being normally held at a predetermined first voltage state by connecting said node (163) to said second, grounded, terminal thereof, whereby said application of a voltage in excess of five volts results in said transistor (156) being gated open and causes said resistance element (162) to be destroyed and said ROM-disable node (163) to change to a second voltage; and means (170, 200), connected to said output (152) of said disabling means (150) and to a mode input (172), for accessing external memory.
Claim 3
Dependent Claim
58 words
A microcomputer according to claim 1, wherein said at least two modes include a single-chip mode in which said central processing unit (100) accesses only said on-chip read-only memory (155) and a fully expanded mode in which said on-chip read-only memory (155) is disabled by said disabling means (150), and said central processing unit (100) accesses external memory.
Claim 4
Dependent Claim
77 words
a microcomputer according to claim 2, in which said disabling means (150) responds to a high voltage applied to said external pin (102), of said microcomputer, connected over a first connecting line (106) to an input of a high voltage detection circuit (110) that applies voltage over a second connecting line (154) to a gate of said high-current capacity transistor (156) that, in turn, applies a high current to said first terminal of said resistance element (162).
Claim 5
Dependent Claim
56 words
A microcomputer according to claim 3, in which said means (170, 200) for accessing external memory responds to said second voltage on said ROM-disable node (163) in such a manner that any signal on said mode input (172) is rendered ineffective, whereby said memory access mode is forced to one of said at least two modes.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-09-01 | 1990-03-03 | 1990-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-09-01 | 1994-03-03 | 1994-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-09-01 | 1998-03-03 | 1998-09-02 | $7700.00 | Window Closed / Lapsed |