Semiconductor dynamic memory device with metal-level selection of page mode or nibble mode

Claim 2

A semiconductor dynamic read/write memory device manufactured to provide either page mode or nibble mode of operation, but not both, comprising: a memory array with rows and columns of cells, row addressing means for selecting a row of cells in response to a row address and a row address strobe signal, column addressing means for selecting a plurality of columns of cells in response to a column address and a column address strobe signal, data input/output means coupled to said column addressing means to input or output data selected among said plurality of columns, and selector means for selecting between page mode of operation and nibble mode of operation, said selector means including clock circuitry for coupling said column address strobe signal to said data input/output means, said selector means rendering a clock to be either responsive or non-responsive to toggling of said column address strobe signal, wherein said clock is rendered either responsive or non-responsive by a single conductor-level connection in manufacture.

Claim 3

A device according to claim 1 wherein said conductor-level connection is a metal-level connection which causes a node to either be discharged by said column address strobe signal, or unresponsive to said column address strobe signal.

Claim 4

A semiconductor memory device manufactured to provide either page mode or nibble mode of operation, but not both, comprising: a memory array with rows and columns of cells, row addressing means for selecting a row of cells in response to a row address and a row address strobe signal, column addressing means for selecting a plurality of columns of cells in response to a column address and a column address strobe signal, data output means coupled to said column addressing means to output data selected from said plurality of columns, and selector means for selecting between page mode of operation and nibble mode of operation, said selector means including clock circuitry for coupling said column address strobe signal to said data input/output means, said selector means rendering a clock to be either responsive or non-responsive to toggling of said column address strobe signal, wherein said clock is rendered responsive or non-responsive by a single conductor-level connection.

Claim 5

A semiconductor memory device manufactured to provide either page mode or nibble mode of operation, but not both, comprising: a memory array with rows and columns of cells, row addressing means for selecting a row of cells in response to a row address and a row address strobe signal, column addressing means for selecting a plurality of columns of cells in response to a column address and a column address strobe signal, data output means coupled to said column addressing means to output data selected from said plurality of columns, and selector means for selecting between page mode of operation and nibble mode of operation, said selector means including clock circuitry for coupling said column address strobe signal to said data input/output means, said selector means rendering a clock to be either responsive or non-responsive to toggling of said column address strobe signal, wherein said clock is rendered responsive or non-responsive by a single conductor-level connection.

Claim 6

A device according to claim 3, wherein said conductor-level connection is a metal-level connection which causes a node to be either discharged by said column address strobe signal, or unresponsive to said column address strobe signal.

Claim 7

A memory device manufactured to provide either a first mode or second mode of operation, but not both, comprising: an array of cells, first addressing means for selecting cells in response to a first address and first control signal, second addressing means for selecting a plurality of cell outputs in response to a second address and a second control signal, data output means coupled to said second addressing means to output data selected among said plurality of cell outputs, and selector means for selecting between said first mode of operation and second mode of operation, said selector means including circuitry for coupling said second control signal to said data output means, said selector means rendering a clock to be either responsive or non-responsive to change of said second control, said clock being rendered either responsive or non-responsive by a single conductor-level connection.

Claim 8

A memory device manufactured to provide either a first mode or second mode of operation, but not both, comprising: an array of cells, first addressing means for selecting cells in response to a first address and first control signal, second addressing means for selecting a plurality of cell outputs in response to a second address and a second control signal, data output means coupled to said second addressing means to output data selected among said plurality of cell outputs, and selector means for selecting between said first mode of operation and second mode of operation, said selector means including circuitry for coupling said second control signal to said data output means, said selector means rendering a clock to be either responsive or non-responsive to change of said second control, said clock being rendered either responsive or non-responsive by a single conductor-level connection.

Claim 9

A device according to claim 5 wherein said conductor-level connection is a metal-level connection which causes a node to be discharged by said second control signal, or unresponsive to said second control signal.

Claim 10

A semiconductor memory device manufactured to provide either page mode or nibble mode of operation, but not both modes of operation, said device comprising: a plurality of memory cells formed in an addressable array with row lines and column lines; a row decoder for selecting cells along a row line in response to a row address and a row address strobe signal; column address circuitry for selecting cells along a plurality of column lines in response to a column address and a column address strobe signal; data output circuitry coupled to said column address circuitry to output data from selected cells along the plurality of column lines; and selection circuitry, providing either page mode of operation or nibble mode of operation, including clock circuitry coupling said column address strobe signal to said data output circuitry, said selection circuitry rendering a clock either responsive or non-responsive to toggling of said column address strobe signal, wherein said clock is rendered either responsive or nonresponsive by a single conductor-level connection.

Claim 11

A semiconductor memory device manufactured to provide either page mode or nibble mode of operation, but not both modes of operation, said device comprising: a plurality of memory cells formed in an addressable array with row lines and column lines; a row decoder for selecting cells along a row line in response to a row address and a row address strobe signal; column address circuitry for selecting cells along a plurality of column lines in response to a column address and a column address strobe signal; data output circuitry coupled to said column address circuitry to output data from selected cells along the plurality of column lines; and selection circuitry, providing either page mode of operation or nibble mode of operation, including clock circuitry coupling said column address strobe signal to said data output circuitry, said selection circuitry rendering a clock either responsive or non-responsive to toggling of said column address strobe signal, wherein said clock is rendered either responsive or nonresponsive by a single conductor-level connection.

Claim 12

The device according to claim 7, wherein said conductor-level connection is a metal level connection which causes a node to either be discharged by said column address strobe signal or nonresponsive to said column address strobe signal.

Claim 13

A semiconductor memory device operable in the page mode or the nibble mode comprising: a plurality of memory cells formed in an addressable array with row lines and column lines; a row decoder for selecting cells along row lines in response to row address information and row address strobe signals; and column address circuitry for selecting cells along a plurality of column lines in response to column address information and column address strobe signals, said circuitry including a selection circuit for rendering said device operable in either the page mode or the nibble mode, said selection circuit comprising an input mode for effecting transfer of address signals into the column address circuitry in response to a series of column address strobe signals provided after each row address strobe signal, said input node chargeable according to a first clock signal derivable from the column address strobe signal, dischargeable according to a second clock signal derivable from the row address strobe signal and also dischargeable according to column address strobe signal, said input node operable to provide either the page mode or the nibble mode, said selection circuit including a first selectable connection for discharging said node in response to each in a series of address strobe signals; and a second selectable connection for rendering the column address circuitry nonresponsive to column address strobe signals after receiving a first signal in each series of column address strobe signals.

Claim 14

A semiconductor memory device operable in the page mode or the nibble mode comprising: a plurality of memory cells formed in an addressable array with row lines and column lines; a row decoder for selecting cells along row lines in response to row address information and row address strobe signals; and column address circuitry for selecting cells along a plurality of column lines in response to column address information and column address strobe signals, said circuitry including a selection circuit for rendering said device operable in either the page mode or the nibble mode, said selection circuit comprising an input mode for effecting transfer of address signals into the column address circuitry in response to a series of column address strobe signals provided after each row address strobe signal, said input node chargeable according to a first clock signal derivable from the column address strobe signal, dischargeable according to a second clock signal derivable from the row address strobe signal and also dischargeable according to column address strobe signal, said input node operable to provide either the page mode or the nibble mode, said selection circuit including a first selectable connection for discharging said node in response to each in a series of address strobe signals; and a second selectable connection for rendering the column address circuitry nonresponsive to column address strobe signals after receiving a first signal in each series of column address strobe signals.

Claim 15

The semiconductor memory device of claim 9 wherein the second selectable connection renders the input node dischargeable according to the inverse value of the first clock signal.

Claim 16

The semiconductor memory device of claim 9 wherein selection between the page mode and the nibble mode of operation is effected by formation of either the first or second connection during manufacture of said device.

Claim 17

The semiconductor memory device of claim 9 wherein selection between page mode and nibble mode of operation is effected by forming one of the selectable connections with a single conductor-level option.

Claim 18

The semiconductor memory device of claim 12 wherein the single conductor-level option is only selectable during device manufacture.

Claim 19

The semiconductor memory device of claim 9 wherein the conductor level option is a metal-level interconnect.

Claim 20

The semiconductor memory device of claim 9 wherein operation is dedicated to either the page or nibble mode during manufacture by formation of either the first or second connection.

Claim 21

The semiconductor memory device of claim 9 wherein said selection circuit further comprises: a first transistor connected to provide a charging current to said input node in response to the first clock signal; a second transistor connected to discharge said input node in response to the second clock signal; a third transistor connectable to discharge said input node in response to column address strobe signals to effect the page mode of operation; and a fourth transistor having a first electrode connected to receive column address strobe signals, a second terminal connected to control current flow through the third transistor and a third terminal connected to effect either the page mode or the nibble mode of operation.

Claim 22

The semiconductor memory device of claim 16 further comprising an inverter having an input connected to said input node and wherein: the page mode of operation is effected by connection of the third terminal of the fourth transistor to a voltage level which renders the fourth transistor conductive; or the nibble mode of operation is effected by connection of the third terminal of the fourth transistor to an output signal of the inverter.

Claim 23

The semiconductor memory device of claim 17 wherein the inverter output provides a third clock signal which is substantially the inverse of the first clock signal.

Claim 24

The semiconductor memory device of claim 17 further comprising a fifth transistor having a first electrode connected to the third terminal of the fourth transistor and second and third terminals both connected to the second terminal of the third transistor.

Claim 25

The semiconductor memory device of claim 16 wherein all of the transistors are field effect transistors.

Claim 26

The semiconductor memory device of claim 16 wherein connection of the third terminal of the fourth transistor to select either the page mode or the nibble mode of operation is effected during manufacture of said memory device.

Claim 27

A circuit for selecting either the page or nibble mode of operation in a semiconductor memory device of the type formed with an array of addressable memory cells, a row decoder and a column decoder and a column clock chain, said circuit comprising: a charging transistor having a first terminal for receiving a voltage level, a second terminal for charging an input node and a third terminal for controlling charge of the input node according to a first clock signal, wherein the first clock signal is derivable from a column address strobe signal; a second transistor connected to discharge the input node in response to a second clock signal; a third transistor connectable to discharge the input node in response to column address strobe signals; and a fourth transistor having a first electrode connected to receive column address strobe signals, a second terminal connected to control discharge of the input node through the third transistor and a third terminal for selectively passing column address strobe signals to the third transistor wherein signals developed at the input node are coupled to control latching of column address signals and reading of data according to either the column mode or the page mode of operation.

Claim 28

A circuit for selecting either the page or nibble mode of operation in a semiconductor memory device of the type formed with an array of addressable memory cells, a row decoder and a column decoder and a column clock chain, said circuit comprising: a charging transistor having a first terminal for receiving a voltage level, a second terminal for charging an input node and a third terminal for controlling charge of the input node according to a first clock signal, wherein the first clock signal is derivable from a column address strobe signal; a second transistor connected to discharge the input node in response to a second clock signal; a third transistor connectable to discharge the input node in response to column address strobe signals; and a fourth transistor having a first electrode connected to receive column address strobe signals, a second terminal connected to control discharge of the input node through the third transistor and a third terminal for selectively passing column address strobe signals to the third transistor wherein signals developed at the input node are coupled to control latching of column address signals and reading of data according to either the column mode or the page mode of operation.

Claim 29

The circuit of claim 22 wherein signals developed at the input node are coupled through an inverter to control the latching of column address signals and reading of data and wherein: the page mode of operation is effected by connection of the third terminal of the fourth transistor to a voltage level which renders the fourth transistor conductive; or the nibble mode of operation is effected by connection of the third terminal of the fourth transistor to the output of the inverter.

Claim 30

The circuit of claim 23 wherein the inverter comprises: a push-pull output stage having a pull-up field effect transistor in series with a pull-down field effect transistor and a node common to said output stage transistors, said common node providing the inverter output signal, said pull-down transistor having a gate electrode coupled to the input node; a second push-pull inverter stage for driving the gate of the pull-up transistor in the output stage, said second stage including a second pull-up field effect transistor in series with a second pull-down field effect transistor and a second node common to said second transistors, said second pull-down transistor having a gate electrode coupled to the input node, said second common node coupled to the gate of the pull-up transistor in the output stage; and booting circuitry coupled to the second common node and coupled to the gate of the second pull-up transistor.

Claim 31

The circuit of claim 24 wherein signals generated by the inverter are substantially in phase with column address strobe signals.

Claim 34

The method of claim 26 further comprising the step of again connecting the input node to the reference potential in response to a signal in the series derivable from row address strobe signals.

Claim 35

The method of claim 27 comprising the additional step of maintaining the input node disconnected from the reference potential between connections which are formed in response to the signals derivable from the row address strobe signals, said additional step providing the nibble mode of operation.

Claim 36

The method of claim 27, comprising the additional step of cyclically connecting the input node to the reference potential between connections which are formed in response to the signals derivable from the row address strobe signals, each cyclic connection effected by a signal in the series derivable from the column address strobe signals, said additional step providing the page mode of operation.