Method of manufacturing a semiconductor integrated circuit device having single-element type non-volatile memory elements

Claim 1

A method of manufacturing a semiconductor memory device including a memory cell, comprising the steps of: (a) providing a semiconductor substrate having a main surface, with a first gate insulating film formed on said main surface, a floating gate electrode formed on said first gate insulating film, a second gate insulating film formed on said floating gate electrode, and a control gate electrode formed on said second gate insulating film; (b) introducing an impurity in self-alignment with one end portion of said control gate electrode to form a first semiconductor region in said semiconductor substrate; and (c) introducing an impurity in self-alignment with another, opposing end portion of said control gate electrode, by using a dose lower than the dose introduced in said step (b), to form a second semiconductor region in said semiconductor substrate, wherein said second semiconductor region has the same conductivity type as said first semiconductor region, wherein, in said step (b), said impurity is selectively introduced into said semiconductor substrate by using a mask layer which covers a portion of said main surface where said second semiconductor region is to be formed, and wherein carriers stored in said floating gate electrode are transferred from said floating gate electrode to said first semiconductor region by tunneling through said first gate insulating film.

Claim 2

A method of manufacturing a semiconductor memory device including a memory cell, comprising the steps of: (a) providing a semiconductor substrate having a main surface, with a first gate insulating film formed on said main surface, a floating gate electrode formed on said first gate insulating film, a second gate insulating film formed on said floating gate electrode, and a control gate electrode formed on said second gate insulating film; (b) introducing an impurity in self-alignment with one end portion of said control gate electrode to form a first semiconductor region in said semiconductor substrate; and (c) introducing an impurity in self-alignment with another, opposing end portion of said control gate electrode, by using a dose lower than the dose introduced in said step (b), to form a second semiconductor region in said semiconductor substrate, wherein said second semiconductor region has the same conductivity type as said first semiconductor region, wherein, in said step (b), said impurity is selectively introduced into said semiconductor substrate by using a mask layer which covers a portion of said main surface where said second semiconductor region is to be formed, and wherein carriers stored in said floating gate electrode are transferred from said floating gate electrode to said first semiconductor region by tunneling through said first gate insulating film.

Claim 12

A method of manufacturing a semiconductor memory device including a memory cell and a MISFET for a peripheral circuit, comprising the steps of: (a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film formed on said memory cell forming region, a floating gate electrode formed on said first gate insulating film, a second gate insulating film formed on said floating gate electrode, and a control gate electrode formed on said second gate insulating film, and with a third gate insulating film formed on said peripheral circuit forming region, a first gate electrode of said MISFET formed on said third gate insulating film; (b) introducing an impurity into said memory cell forming region in self-alignment with one end portion of said control gate electrode to form a first semiconductor region in said semiconductor substrate; (c) introducing an impurity into said memory cell forming region in self-alignment with another, opposing end portion of said control gate electrode, by using a dose lower than the dose introduced in said step (b), to form a second semiconductor region in said semiconductor substrate; (d) introducing an impurity into said peripheral circuit forming region in self-alignment with said first gate electrode, by using a dose lower than the dose introduced in said step (b), to form a third semiconductor region in said semiconductor substrate, (e) after said steps (b), (c) and (d), forming first side wall spacers on both of side surfaces of said control and floating gate electrodes in self-alignment with said control and floating gate electrodes, and forming second side wall spacers on side surfaces of said first gate electrode; and (f) introducing an impurity into said peripheral circuit forming region in self-alignment with said second side wall spacers, by using a dose higher than the dose introduced in said step (d), to form a fourth semiconductor region in said semiconductor substrate, wherein said fourth semiconductor region has the same conductivity type as said first, second and third semiconductor regions, wherein said third and fourth semiconductor regions together serve as a drain region of said MISFET, and wherein carriers stored in said floating gate electrode are transferred from said floating gate electrode to said first semiconductor region by tunneling through said first gate insulating film.

Claim 13

A method of manufacturing a semiconductor memory device including a memory cell and a MISFET for a peripheral circuit, comprising the steps of: (a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film formed on said memory cell forming region, a floating gate electrode formed on said first gate insulating film, a second gate insulating film formed on said floating gate electrode, and a control gate electrode formed on said second gate insulating film, and with a third gate insulating film formed on said peripheral circuit forming region, a first gate electrode of said MISFET formed on said third gate insulating film; (b) introducing an impurity into said memory cell forming region in self-alignment with one end portion of said control gate electrode to form a first semiconductor region in said semiconductor substrate; (c) introducing an impurity into said memory cell forming region in self-alignment with another, opposing end portion of said control gate electrode, by using a dose lower than the dose introduced in said step (b), to form a second semiconductor region in said semiconductor substrate; (d) introducing an impurity into said peripheral circuit forming region in self-alignment with said first gate electrode, by using a dose lower than the dose introduced in said step (b), to form a third semiconductor region in said semiconductor substrate, (e) after said steps (b), (c) and (d), forming first side wall spacers on both of side surfaces of said control and floating gate electrodes in self-alignment with said control and floating gate electrodes, and forming second side wall spacers on side surfaces of said first gate electrode; and (f) introducing an impurity into said peripheral circuit forming region in self-alignment with said second side wall spacers, by using a dose higher than the dose introduced in said step (d), to form a fourth semiconductor region in said semiconductor substrate, wherein said fourth semiconductor region has the same conductivity type as said first, second and third semiconductor regions, wherein said third and fourth semiconductor regions together serve as a drain region of said MISFET, and wherein carriers stored in said floating gate electrode are transferred from said floating gate electrode to said first semiconductor region by tunneling through said first gate insulating film.

Claim 25

A method of manufacturing a semiconductor memory device including a memory cell and an MISFET for a peripheral circuit, comprising steps of: (a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film formed on said memory cell forming region, a floating gate electrode formed on said first gate insulating film, a second gate insulating film formed on said floating gate electrode, and a control gate electrode formed on said second gate insulating film, and with a third gate insulating film formed on said peripheral circuit forming region, a first gate electrode of said MISFET formed on said third gate insulating film; (b) forming a first semiconductor region in said memory cell forming region by introducing an impurity into said memory cell forming region in self-alignment with one end portion of said control gate electrode; (c) forming a second semiconductor region in said memory cell forming region by introducing an impurity into said memory cell forming region in self-alignment with another end portion of said control gate electrode, wherein said first semiconductor region and said second semiconductor region are formed so as to be extended under said floating gate electrode, wherein said first semiconductor region has the same conductivity type as said second semiconductor region, and wherein a dose introduced in said step (c) is lower than a dose introduced in said step (b); (d) after introduction of said impurities in said step (b) and said step (c), depositing a first insulating film on said control gate electrode and said first gate electrode so as to cover said memory cell forming region and said peripheral circuit forming region; and (e) etching said first insulating film to form first side wall spacers on both of side surfaces of said control and floating gate electrodes in self-alignment with said control and floating gate electrodes and to form second side wall spacers on side surfaces of said first gate electrode, wherein carriers are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.

Claim 26

A method of manufacturing a semiconductor memory device including a memory cell and an MISFET for a peripheral circuit, comprising steps of: (a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film formed on said memory cell forming region, a floating gate electrode formed on said first gate insulating film, a second gate insulating film formed on said floating gate electrode, and a control gate electrode formed on said second gate insulating film, and with a third gate insulating film formed on said peripheral circuit forming region, a first gate electrode of said MISFET formed on said third gate insulating film; (b) forming a first semiconductor region in said memory cell forming region by introducing an impurity into said memory cell forming region in self-alignment with one end portion of said control gate electrode; (c) forming a second semiconductor region in said memory cell forming region by introducing an impurity into said memory cell forming region in self-alignment with another end portion of said control gate electrode, wherein said first semiconductor region and said second semiconductor region are formed so as to be extended under said floating gate electrode, wherein said first semiconductor region has the same conductivity type as said second semiconductor region, and wherein a dose introduced in said step (c) is lower than a dose introduced in said step (b); (d) after introduction of said impurities in said step (b) and said step (c), depositing a first insulating film on said control gate electrode and said first gate electrode so as to cover said memory cell forming region and said peripheral circuit forming region; and (e) etching said first insulating film to form first side wall spacers on both of side surfaces of said control and floating gate electrodes in self-alignment with said control and floating gate electrodes and to form second side wall spacers on side surfaces of said first gate electrode, wherein carriers are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.