Patent US5625220A successfully refreshed from Google Patents.
US5625220A
Expired / Lapsed
US
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Sublithographic antifuse
Assignee: Texas Instruments Inc
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Filing: 1994-08-08
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Granted: 1997-04-29
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Expires: 2014-08-08
Abstract
Abstract This antifuse includes: a sublithographic conductive pattern (18); an antifuse material (24) overlying said sublithographic conductive pattern (18); and a conductive layer (26) overlying the antifuse material (24) to form a reduced area antifuse (10). Other devices, systems and methods are also disclosed.
Inventors
- 👤 David K.-Y. Liu
- 👤 Kueing-Long Chen
- 👤 Bert R. Riemenschneider
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-10 02:23
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
107 words
A sublithographic semiconductor antifuse, said antifuse comprising: a substrate; a horizontally sublithographic conductive pattern overlying and distinct from said substrate, the entire breadth of at least one dimension of said sublithographic conductive pattern being less than a minimum lithographic feature size and wherein said horizontally sublithographic conductive pattern includes substantially vertical sidewalls; an antifuse material overlying said horizontally sublithographic conductive pattern; a conductive layer over said antifuse material whereby an antifusing area is formed between said horizontally sublithographic conductive pattern and said conductive layer; and a sidewall insulator material on at least one of said sidewalls of said horizontally sublithographic conductive pattern and underlying said antifuse material.
Claim 2
Dependent Claim
107 words
A sublithographic semiconductor antifuse, said antifuse comprising: a substrate; a horizontally sublithographic conductive pattern overlying and distinct from said substrate, the entire breadth of at least one dimension of said sublithographic conductive pattern being less than a minimum lithographic feature size and wherein said horizontally sublithographic conductive pattern includes substantially vertical sidewalls; an antifuse material overlying said horizontally sublithographic conductive pattern; a conductive layer over said antifuse material whereby an antifusing area is formed between said horizontally sublithographic conductive pattern and said conductive layer; and a sidewall insulator material on at least one of said sidewalls of said horizontally sublithographic conductive pattern and underlying said antifuse material.
Claim 3
Dependent Claim
12 words
The antifuse of claim 1 wherein said antifuse material is an oxide.
Claim 4
Dependent Claim
60 words
The antifuse of claim 1 wherein said antifuse material is comprised of a first dielectric layer overlying said conductive pattern, said first dielectric layer comprising a first material and a second dielectric layer overlying said first dielectric layer, said second dielectric layer comprising a second material such that said antifuse material formed thereby will have an asymmetric current conduction characteristic.
Claim 5
Dependent Claim
25 words
The antifuse of claim 3 wherein one of said first and second materials is an oxide and the other of said materials is a nitride.
Claim 6
Dependent Claim
11 words
The antifuse of claim 1 wherein said substrate is an insulator.
Claim 7
Dependent Claim
71 words
A sublithographic semiconductor antifuse, said antifuse comprising: a) a substrate; b) a horizontally sublithographic polysilicon conductive pattern overlying said substrate, said conductive pattern having substantially vertical sidewalls; c) a sidewall oxide about a perimeter of said conductive pattern; d) a nitride-oxide asymmetric antifuse material overlying said conductive pattern; e) a polysilicon conductive layer over said antifuse material whereby an antifusing area is formed between said conductive pattern and said conductive layer.
Claim 8
Dependent Claim
71 words
A sublithographic semiconductor antifuse, said antifuse comprising: a) a substrate; b) a horizontally sublithographic polysilicon conductive pattern overlying said substrate, said conductive pattern having substantially vertical sidewalls; c) a sidewall oxide about a perimeter of said conductive pattern; d) a nitride-oxide asymmetric antifuse material overlying said conductive pattern; e) a polysilicon conductive layer over said antifuse material whereby an antifusing area is formed between said conductive pattern and said conductive layer.
Claim 9
Dependent Claim
30 words
The antifuse of claim 6 wherein a voltage is applied across said conductive pattern and said conductive layer to breakdown said antifuse material and render said antifuse material conductive therebetween.
Claim 10
Dependent Claim
56 words
The antifuse of claim 7 wherein a first voltage of a first polarity must be applied across the antifuse to breakdown said antifuse and wherein a second voltage of the opposite polarity from said first polarity must be applied across the antifuse to breakdown said antifuse, said second voltage being substantially different from said first voltage.
Claim 11
Dependent Claim
13 words
The antifuse of claim 7 wherein conductive pattern is a silicided polysilicon material.
Claim 12
Dependent Claim
12 words
The antifuse of claim 7 wherein said substrate is a crystalline semiconductor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-28 | 2000-10-28 | 2001-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-28 | 2004-10-28 | 2005-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-28 | 2008-10-28 | 2009-04-29 | $7700.00 | Window Closed / Lapsed |