US5616512A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power semiconductor devices
Assignee: CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
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Filing: 1994-12-21
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Granted: 1997-04-01
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Expires: 2014-12-21
Abstract
Abstract A process for manufacturing integrated circuits includes the following steps. First, an oxide layer is formed on at least one surface of two respective semiconductor material wafers. Next, a single semiconductor material wafer is obtained with a first layer and a second layer of semiconductor material and a buried oxide layer interposed therebetween starting from said two semiconductor material wafers by direct bonding of the oxide layers previously grown. The single wafer is submitted to a controlled reduction of the thickness of the first layer of semiconductor material and the top surface of the first layer of semiconductor material is lapped. Dopant impurities are selectively introduced into selected regions of the first layer of semiconductor material to form the desired integrated components. Trenches are formed laterally delimiting respective portions of the first layer of semiconductor material wherein integrated components are present which are to be electrically isolated from other integrated components. Finally the walls of the trenches are coated with an insulating material and filled with amorphous silicon.
Inventors
- 👤 Cesare Ronsisvalle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 20:10
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/201; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D86/01; H10D88/00; H10D88/01; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10P90/1914; H10W10/041; H10W10/40; Y; Y10; Y10S; Y10S148/00; Y10S148/012; Y10S148/05
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
242 words
A method of manufacturing integrated circuits, comprising the steps of: forming an oxide layer on at least one surface of two respective semiconductor material wafers; obtaining a single semiconductor material wafer with a first layer and a second layer of semiconductor material and a buried oxide layer interposed therebetween starting from the two semiconductor material wafers by direct bonding together the oxide layers; submitting the single wafer to a controlled reduction of a thickness of the first layer of semiconductor material; lapping a top surface of the first layer of semiconductor material; selectively etching the first layer of semiconductor material down to the buried oxide layer to obtain selected portions of the single wafer wherein the buried oxide layer is uncovered; selectively introducing first dopant impurities into selected regions of the second layer of semiconductor material without introducing the first dopant impurities into the first layer of semiconductor material; selectively introducing second dopant impurities into selected regions of the first layer of semiconductor material to form integrated components; forming an insulating material layer over the top surface of the first layer of semiconductor material; selectively etching the insulating material layer and the first layer of semiconductor material down to the buried oxide layer to form trenches laterally delimiting respective portions of the first layer of semiconductor material such that each integrated component is electrically isolated; coating the walls of the trenches with an insulating material; and filling the trenches with amorphous silicon.
Claim 2
Independent Claim
242 words
A method of manufacturing integrated circuits, comprising the steps of: forming an oxide layer on at least one surface of two respective semiconductor material wafers; obtaining a single semiconductor material wafer with a first layer and a second layer of semiconductor material and a buried oxide layer interposed therebetween starting from the two semiconductor material wafers by direct bonding together the oxide layers; submitting the single wafer to a controlled reduction of a thickness of the first layer of semiconductor material; lapping a top surface of the first layer of semiconductor material; selectively etching the first layer of semiconductor material down to the buried oxide layer to obtain selected portions of the single wafer wherein the buried oxide layer is uncovered; selectively introducing first dopant impurities into selected regions of the second layer of semiconductor material without introducing the first dopant impurities into the first layer of semiconductor material; selectively introducing second dopant impurities into selected regions of the first layer of semiconductor material to form integrated components; forming an insulating material layer over the top surface of the first layer of semiconductor material; selectively etching the insulating material layer and the first layer of semiconductor material down to the buried oxide layer to form trenches laterally delimiting respective portions of the first layer of semiconductor material such that each integrated component is electrically isolated; coating the walls of the trenches with an insulating material; and filling the trenches with amorphous silicon.
Claim 3
Dependent Claim
103 words
A method of manufacturing integrated circuits according to claim 1, further comprising the steps of: removing the insulating layer from the top surface of the first semiconductor materials; planarizing the top surface of the first semiconductor material; growing a thermal oxide layer over the top surface of the first semiconductor material; selectively etching the thermal oxide layer to form contact areas; depositing aluminum over a top surface of the thermal oxide layer and a top surface of the first semiconductor materials to form an aluminum layer; and selectively etching the aluminum layer to form a pattern of interconnection lines between the integrated components.
Claim 4
Dependent Claim
11 words
The method according to claim 2 wherein the trenches are v-shaped.
Claim 5
Dependent Claim
18 words
The method according to claim 2 wherein a base of the trenches extends to the buried oxide layer.
Claim 6
Dependent Claim
17 words
The method according to claim 2, further comprising a contact layer disposed above the doped semiconductor regions.
Claim 7
Dependent Claim
26 words
The method according to claim 5, further comprising an oxide layer disposed above the electrically isolated portions everywhere except for where there is a contact layer.
Claim 8
Dependent Claim
24 words
The method according to claim 6 wherein a top surface of the contact layer and a top surface of the oxide layer are flat.
Claim 9
Independent Claim
132 words
A method of isolating an integrated circuit, comprising the steps of: providing a layer of semiconductor material having a first portion and a second portion; disposing an integrated circuit within the first portion of the layer of the semiconductor material without etching an insulating material layer disposed along an outer surface of the first portion of the semiconductor material; disposing the insulating material layer along an outer surface of the first portion and the second portion of the layer of the semiconductor material to form a layer of insulating material; simultaneously etching a notch in the layer of insulating material along the outer surface of the second portion and in the second portion of the layer of the semiconductor material; and depositing insulation material consisting only of an oxide in the notch.
Claim 10
Independent Claim
132 words
A method of isolating an integrated circuit, comprising the steps of: providing a layer of semiconductor material having a first portion and a second portion; disposing an integrated circuit within the first portion of the layer of the semiconductor material without etching an insulating material layer disposed along an outer surface of the first portion of the semiconductor material; disposing the insulating material layer along an outer surface of the first portion and the second portion of the layer of the semiconductor material to form a layer of insulating material; simultaneously etching a notch in the layer of insulating material along the outer surface of the second portion and in the second portion of the layer of the semiconductor material; and depositing insulation material consisting only of an oxide in the notch.
Claim 11
Dependent Claim
29 words
The method according to claim 1, wherein the step of selectively etching the insulating material layer and the first layer of semiconductor material includes forming trenches having a v-shape.
Claim 12
Dependent Claim
27 words
The method according to claim 1, further comprising a step of forming a contact layer disposed above the selected regions of the first layer of semiconductor material.
Claim 13
Dependent Claim
52 words
The method according to claim 1, wherein the step of selectively introducing dopant impurities into selected regions of the first layer of semiconductor material includes using a photolithographic apparatus, and wherein the step of selectively introducing dopant impurities into selected regions of the second layer semiconductor material includes using the photolithographic apparatus.
Claim 14
Dependent Claim
29 words
The method according to claim 1, wherein the step of selectively etching the first layer of semiconductor material includes using a small etching angle to avoid creating high steps.
Claim 15
Dependent Claim
29 words
The method according to claim 2, wherein the step of selectively etching the first layer of semiconductor material includes using a small etching angle to avoid creating high steps.
Claim 16
Dependent Claim
18 words
The method according to claim 8, wherein the step of depositing insulation material includes forming a vertical trench.
Claim 17
Dependent Claim
21 words
The method according to claim 8, wherein the step of depositing insulation material includes forming a vertical trench having a v-shape.
Claim 18
Dependent Claim
69 words
The method according to claim 8, wherein the step of disposing an integrated circuit within the first portion of the layer of semiconductor material includes the steps of: providing a single semiconductor material wafer having a first layer of semiconductor material, a second layer of semiconductor material and a buried oxide layer disposed therebetween; and selectively introducing dopant impurities into selected regions of the first layer of semiconductor material.
Claim 19
Dependent Claim
54 words
The method according to claim 16, further comprising the steps of: selectively etching the first layer of semiconductor material down to the oxide layer to obtain selected portions of the single wafer wherein the oxide layer is uncovered; and selectively introducing dopant impurities into selected regions of the second layer of the semiconductor material.
Claim 20
Dependent Claim
29 words
The method according to claim 17, wherein the step of selectively etching the first layer of semiconductor material includes using a small etching angle to avoid creating high steps.
Claim 21
Independent Claim
145 words
A method of manufacturing an integrated circuit, the method comprising the steps of: providing a semiconductor material wafer having a first layer of semiconductor material, a second layer of semiconductor material and an oxide layer interposed therebetween; selectively etching the first layer of semiconductor material to the oxide layer to uncover selected portions of the oxide layer; introducing first dopant impurities into selected regions of the second layer of semiconductor material without introducing the first dopant impurities into the first layer of semiconductor material; introducing second dopant impurities into selected regions of the first layer of semiconductor material; forming an insulating material layer over an outer surface of the first layer of semiconductor material; selectively etching the insulating material layer and the first layer of semiconductor material to the oxide layer to form trenches; and coating the walls of the trenches with an insulating material.
Claim 22
Independent Claim
145 words
A method of manufacturing an integrated circuit, the method comprising the steps of: providing a semiconductor material wafer having a first layer of semiconductor material, a second layer of semiconductor material and an oxide layer interposed therebetween; selectively etching the first layer of semiconductor material to the oxide layer to uncover selected portions of the oxide layer; introducing first dopant impurities into selected regions of the second layer of semiconductor material without introducing the first dopant impurities into the first layer of semiconductor material; introducing second dopant impurities into selected regions of the first layer of semiconductor material; forming an insulating material layer over an outer surface of the first layer of semiconductor material; selectively etching the insulating material layer and the first layer of semiconductor material to the oxide layer to form trenches; and coating the walls of the trenches with an insulating material.
References Cited (Backward Citations)
US3434019A
Cited
US4001860A
Cited
US3909320A
Cited
US4190850A
Cited
US4305974A
Cited
US4233615A
Cited
US4593302A
Cited
US4593302B1
Cited
US4549193A
Cited
US4682405A
Cited
US4948748A
Cited
US4798810A
Cited
US4766090A
Cited
US5036021A
Cited
US4963505A
Cited
JPH01129439A
Cited
US4985745A
Cited
US4889829A
Cited
US5097314A
Cited
US4908328A
Cited
US5223450A
Cited
EP0543361A2
Cited
US5356827A
Cited
US5342480A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-31 | 2000-09-30 | 2001-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-31 | 2004-09-30 | 2005-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-31 | 2008-09-30 | 2009-04-01 | $7700.00 | Window Closed / Lapsed |