US4766090A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Methods for fabricating latchup-preventing CMOS device
Assignee: Nokia Bell Labs
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Filing: 1986-11-21
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Granted: 1988-08-23
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Expires: 2006-11-21
Abstract
Abstract A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10 μm, as well as a method for fabricating the choice, is disclosed. The inventive device, which is formed in a substrate comprising a relatively heavily doped bulk region supporting a relatively thin, moderately doped layer, includes a polysilicon-filled trench extending through a portion of the layer, between the n- and p-channel FETs of the device. The inventive device also includes a relatively heavily doped region extending from a bottom of the trench to the bulk region. The polysilicon-filled trench, in combination with both the relatively heavily doped region and bulk region, prevents latchup.
Inventors
- 👤 Gerald A. Coquin
- 👤 William T. Lynch
- 👤 Louis C. Parrillo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:13
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/40
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
133 words
A method for fabricating a device, comprising the steps of: forming a trench in a semiconductor substrate which includes a surface, said trench extending from said surface into said substrate; depositing a composition comprising polysilicon into said trench; and completing the fabrication of said device, characterized in that said substrate includes a bulk region supporting a relatively thin layer whose doping level is less than that of said bulk region, said trench extending through a portion of said relatively thin layer, and said method further comprises the step of doping a region of said relatively thin layer, immediately beneath said trench, with dopant after said forming step but before said depositing step, to form a relatively heavily doped region in said layer extending from a bottom of said trench to said bulk region.
Claim 2
Independent Claim
133 words
A method for fabricating a device, comprising the steps of: forming a trench in a semiconductor substrate which includes a surface, said trench extending from said surface into said substrate; depositing a composition comprising polysilicon into said trench; and completing the fabrication of said device, characterized in that said substrate includes a bulk region supporting a relatively thin layer whose doping level is less than that of said bulk region, said trench extending through a portion of said relatively thin layer, and said method further comprises the step of doping a region of said relatively thin layer, immediately beneath said trench, with dopant after said forming step but before said depositing step, to form a relatively heavily doped region in said layer extending from a bottom of said trench to said bulk region.
Claim 3
Dependent Claim
49 words
The method of claim 1 wherein said trench is formed to include a sidewall which, in cross-section, is substantially linear and forms an angle with a perpendicular drawn to said surface at the intersection of said sidewall and said surface ranging from about 5 degrees to about 10 degrees.
Claim 4
Dependent Claim
20 words
The method of claim 1 wherein a thickness of said composition is greater than half the width of said trench.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-23 | 1992-02-22 | 1992-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-23 | 1996-02-22 | 1996-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-23 | 2000-02-22 | 2000-08-23 | $7700.00 | Window Closed / Lapsed |