US5615402A
Expired / Lapsed
US
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Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch
Assignee: VIA Cyrix Inc
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Filing: 1995-12-14
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Granted: 1997-03-25
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Expires: 2015-12-14
Abstract
Abstract A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.
Inventors
- 👤 Marc A. Quattromani
- 👤 Raul A. Garibay, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 06:42
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3004; G06F9/30043; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0855; G06F9/30181; G06F9/38; G06F9/3824; G06F9/3834; G06F9/3836; G06F9/3842; G06F9/3854; G06F9/3858; G06F9/3861; G06F9/3865; G06F12/04
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
226 words
A microprocessor comprising: (a) a first processing unit that processes a first program instruction to produce a first write operand of a predetermined width; (b) a second processing unit that processes a second program instruction to produce a second write operand having a width greater than the predetermined width of the first write operand; (c) an extra wide latch having a width equal to the width of the second write operand and coupled to receive the second write operand from the second processing unit; (d) a unified write buffer having a plurality of entries, coupled to the first processing unit, each of the plurality of entries having a data portion that stores the first write operand, an address portion that stores an address, and a control portion that identifies whether the address belongs to the first write operand or the second write operand in the extra wide latch; (e) a datapath of predetermined width, coupled to the extra wide latch and to the unified write buffer, wherein the width of the extra wide latch is equal to or less than the predetermined width of the datapath; and, (f) a memory coupled to the address portion from the unified write buffer and to the datapath to receive either the first write operand or the second write operand responsive to the control portion of the unified write buffer.
Claim 2
Dependent Claim
226 words
A microprocessor comprising: (a) a first processing unit that processes a first program instruction to produce a first write operand of a predetermined width; (b) a second processing unit that processes a second program instruction to produce a second write operand having a width greater than the predetermined width of the first write operand; (c) an extra wide latch having a width equal to the width of the second write operand and coupled to receive the second write operand from the second processing unit; (d) a unified write buffer having a plurality of entries, coupled to the first processing unit, each of the plurality of entries having a data portion that stores the first write operand, an address portion that stores an address, and a control portion that identifies whether the address belongs to the first write operand or the second write operand in the extra wide latch; (e) a datapath of predetermined width, coupled to the extra wide latch and to the unified write buffer, wherein the width of the extra wide latch is equal to or less than the predetermined width of the datapath; and, (f) a memory coupled to the address portion from the unified write buffer and to the datapath to receive either the first write operand or the second write operand responsive to the control portion of the unified write buffer.
Claim 3
Dependent Claim
26 words
The microprocessor of claim 1 wherein the extra wide latch further includes a control bit for indicating that the second write operand stored therein is valid.
Claim 4
Dependent Claim
16 words
The microprocessor of claim 1 wherein the first processing unit is a integer central processing unit.
Claim 5
Dependent Claim
16 words
The microprocessor of claim 1 wherein the second processing unit is a floating point processing unit.
Claim 6
Dependent Claim
253 words
A microprocessor comprising: (a) first processing means for processing a first program instruction to produce a first write operand of a predetermined width; (b) second processing means for processing a second program instruction to produce a second write operand having a width greater than the predetermined width of the first write operand; (c) extra wide latch means having a width equal to the width of the second write operand, for storing the second write operand; (d) unified write buffer means coupled to the first processing means and having a data portion for receiving the first write operand, an address portion for storing an address, and a control portion for identifying whether the address in the address portion identifies the first write operand in the data portion of the unified write buffer means or the second write operand in the extra wide latch means; (e) datapath means of predetermined width, coupled to the extra wide latch, the unified write buffer, for transferring the first and second write Operands to memory, wherein the width of the extra wide latch means is equal to or less than the predetermined width of the datapath; and, (e) a memory coupled to the extra wide latch means and to the unified write buffer means, for receiving the address portion from the unified write buffer means and data over the datapath means from either the extra wide latch means or the data portion in the unified write buffer means responsive to the control portion in the unified write buffer means.
Claim 7
Dependent Claim
253 words
A microprocessor comprising: (a) first processing means for processing a first program instruction to produce a first write operand of a predetermined width; (b) second processing means for processing a second program instruction to produce a second write operand having a width greater than the predetermined width of the first write operand; (c) extra wide latch means having a width equal to the width of the second write operand, for storing the second write operand; (d) unified write buffer means coupled to the first processing means and having a data portion for receiving the first write operand, an address portion for storing an address, and a control portion for identifying whether the address in the address portion identifies the first write operand in the data portion of the unified write buffer means or the second write operand in the extra wide latch means; (e) datapath means of predetermined width, coupled to the extra wide latch, the unified write buffer, for transferring the first and second write Operands to memory, wherein the width of the extra wide latch means is equal to or less than the predetermined width of the datapath; and, (e) a memory coupled to the extra wide latch means and to the unified write buffer means, for receiving the address portion from the unified write buffer means and data over the datapath means from either the extra wide latch means or the data portion in the unified write buffer means responsive to the control portion in the unified write buffer means.
Claim 8
Dependent Claim
27 words
The microprocessor of claim 5 wherein the extra wide latch means further includes a control bit for indicating that the second write operand stored therein is valid.
Claim 9
Dependent Claim
16 words
The microprocessor of claim 5 wherein the first processing means is an integer central processing unit.
Claim 10
Dependent Claim
16 words
The microprocessor of claim 5 wherein the second processing means is a floating point processing unit.
Claim 11
Dependent Claim
223 words
In a microprocessor having a unified write buffer with a plurality of entries, each entry having a data portion, an address portion, and a control portion, a method of buffering first and second write operands prior to storage in a memory, comprising the steps of: (a) processing a first program instruction to produce a first write operand of a predetermined width; (b) processing a second program instruction to produce a second write operand having a width greater than the predetermined width of the first write operand; (c) receiving the second write operand into an extra wide latch having a width equal to the width of the second write operand; (d) receiving the first write operand into the data portion of one of the plurality of write buffer entries; (e) storing an address into the address portion of one of the plurality of write buffer entries; (f) identifying in the control portion of one of the plurality of write buffer entries, whether the address in the address portion identifies the first write operand or the second operand; and, (g) responsive to the control portion, receiving into a memory, the address portion and either the first write operand or the second write operand over a datapath, wherein the width of the second write operand is equal to or less than a width of the datapath.
Claim 12
Dependent Claim
223 words
In a microprocessor having a unified write buffer with a plurality of entries, each entry having a data portion, an address portion, and a control portion, a method of buffering first and second write operands prior to storage in a memory, comprising the steps of: (a) processing a first program instruction to produce a first write operand of a predetermined width; (b) processing a second program instruction to produce a second write operand having a width greater than the predetermined width of the first write operand; (c) receiving the second write operand into an extra wide latch having a width equal to the width of the second write operand; (d) receiving the first write operand into the data portion of one of the plurality of write buffer entries; (e) storing an address into the address portion of one of the plurality of write buffer entries; (f) identifying in the control portion of one of the plurality of write buffer entries, whether the address in the address portion identifies the first write operand or the second operand; and, (g) responsive to the control portion, receiving into a memory, the address portion and either the first write operand or the second write operand over a datapath, wherein the width of the second write operand is equal to or less than a width of the datapath.
Claim 13
Dependent Claim
30 words
The method of claim 8, further comprising step (h) after step (c), setting a control bit in the extra wide latch to indicate that the second write operand is valid.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-24 | 2000-09-23 | 2001-03-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-24 | 2004-09-23 | 2005-03-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-24 | 2008-09-23 | 2009-03-25 | $7700.00 | Window Closed / Lapsed |