Apparatus and method for simultaneous execution of a write instruction and a succeeding read instruction in a data processing system with a store through cache strategy

Claim 1

A data processing system comprising: a memory unit; a system bus coupled to said memory unit; and a plurality of data processing units coupled to said system bus, wherein said data processing units and said memory unit transfer data operands and associated address operands asynchronously over said system bus, each data processing unit processing a sequence of instructions, said sequence of instruction including read instructions and write instructions, each data processing unit transferring a data operand to said main memory in response to a write instruction, each of said data processing units including: an address unit responsive to said read and write instructions for providing associated address operands for data operands identified by said read instructions and said write instructions; an execution unit responsive to said write instructions for providing data operands for storage in said memory unit at locations identified by associated address operands, wherein determination of a data operand by said execution unit can require a longer time period than providing an associated address operand by said address unit; a cache means coupled to said execution unit for storing data operands at locations determined by said associated address operands, said cache means temporarily storing a write instruction address operand from said address unit in response to a first write instruction while said execution unit determines an associated write instruction date operand in response to said first write instruction, said cache means including apparatus providing a read data operand from a location determined by an associated read address operand to said execution unit in response to a read instruction, wherein a read instruction data operand stored in said cache means can be transferred to said execution unit in response to a first read instruction after a write instruction address operand has been transferred to said cache unit and before an associated write instruction data operand has been transferred to said cache means, initiation of processing of said firs read instruction following initiation of processing of said first write instruction by said data processing unit, wherein said cache means apparatus includes busy means for preventing transfer of a read instruction data operand to said execution unit by said cache means until determination of a write instruction data operand when said associated read instruction address operand is identical to said associated write instruction address operand; and an interface unit receiving write instruction data operands and associated write instruction address operands from said cache means, said interface unit applying said write data operands and associated write instruction address operands from said cache means to said system bus for transfer to said memory unit.

Claim 8

A method of expediting instruction execution in a data processing system having at least one pipelined data processing unit and a memory unit asynchronously coupled to a system bus, wherein said data processing units include cache units having a store through strategy, wherein said data processing units execute sequences of instructions including read instructions and write instructions, said method comprising the steps of: storing a write address operand determined by a write instruction in a cache unit while an execution unit is determining an associated write data operand; transferring a read data operand identified by a read address operand applied to said execution unit as a result of a read instruction processed following said write instruction, said read data operand being transferred to said execution unit after storing said write address operand and before transferring said associated write data operand to said cache unit for transfer to said memory unit; comparing said read address operand with said stored write address operand; preventing transfer of said read data operand from said cache unit to said execution unit until said write data operand has been transferred to said cache unit; transferring a second read data operand to said execution unit in response to a second read instruction following said write instruction prior to transfer of said write data operand to said cache unit; and transferring said associated write address operand to said cache unit.

Claim 9

A method of expediting instruction execution in a data processing system having at least one pipelined data processing unit and a memory unit asynchronously coupled to a system bus, wherein said data processing units include cache units having a store through strategy, wherein said data processing units execute sequences of instructions including read instructions and write instructions, said method comprising the steps of: storing a write address operand determined by a write instruction in a cache unit while an execution unit is determining an associated write data operand; transferring a read data operand identified by a read address operand applied to said execution unit as a result of a read instruction processed following said write instruction, said read data operand being transferred to said execution unit after storing said write address operand and before transferring said associated write data operand to said cache unit for transfer to said memory unit; comparing said read address operand with said stored write address operand; preventing transfer of said read data operand from said cache unit to said execution unit until said write data operand has been transferred to said cache unit; transferring a second read data operand to said execution unit in response to a second read instruction following said write instruction prior to transfer of said write data operand to said cache unit; and transferring said associated write address operand to said cache unit.