EP0348652A2
Expired / Lapsed
EP
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Checkpoint retry system
Assignee: International Business Machines Corp
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Filing: 1989-05-17
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Granted: —
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Expires: 2009-05-17
Abstract
Abstract A checkpoint retry system for recovery from an error condition in a multiprocessor type central processing unit which may have a store-in or a store-through cache system. At detection of a checkpoint instruction, the system initiates action to save the content of the program status word, the floating point registers, the access registers and the general purpose registers until the store operations are completed for the checkpointed sequence. For processors which have a store-in cache, modified cache data is saved in a store buffer until the checkpointed instructions are completed and then written to a cache which is accessible to other processors in the system. For processors which utilize store-through cache, the modified data for the checkpointed instructions is also stored in the store buffer prior to storage in the system memory.
Inventors
- 👤 Barbara Ann Hall
- 👤 Kevin Chuang-Chi Huang
- 👤 John David Jabusch
- 👤 Agnes Yee Ngai
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 12:13
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1405; G06F11/1407; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0811
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
180 words
Checkpoint retry storage subsystem for use in a data processing system having a store-in level two cache or store-through level one cache between an instruction processing unit and a L3 main storage unit, including means for generating a retry signal in response to erroneous execution of an instruction by said system, characterized by means responsive to selected instructions for developing a checkpoint signal; by a program status word stack storage for storing program status words; by a general purpose register storage for storing the data content of selected registers in said data processing system; by a data storage comprising a L1 store buffer located between said instruction processing unit and L3 memory; and, by checkpoint storage control means responsive to said checkpoint signal and connected to control said program status word storage, said general register storage and said store buffer for storing the current program status word in said program status word storage, for storing the content of said selected registers in said general purpose register storage and for storing data associated with said checkpointed instruction in said write buffer.
Claim 2
Dependent Claim
180 words
Checkpoint retry storage subsystem for use in a data processing system having a store-in level two cache or store-through level one cache between an instruction processing unit and a L3 main storage unit, including means for generating a retry signal in response to erroneous execution of an instruction by said system, characterized by means responsive to selected instructions for developing a checkpoint signal; by a program status word stack storage for storing program status words; by a general purpose register storage for storing the data content of selected registers in said data processing system; by a data storage comprising a L1 store buffer located between said instruction processing unit and L3 memory; and, by checkpoint storage control means responsive to said checkpoint signal and connected to control said program status word storage, said general register storage and said store buffer for storing the current program status word in said program status word storage, for storing the content of said selected registers in said general purpose register storage and for storing data associated with said checkpointed instruction in said write buffer.
Claim 3
Dependent Claim
67 words
Checkpoint retry storage subsystem according to claim 1, characterized in that the checkpoint storage control means is responsive to the retry signal to fetch the program status word, the content of the general purpose registers and the data stored at the immediately preceding checkpoint and load said program status word, said register content and said data into the location from which it was taken at said checkpoint.
Claim 4
Dependent Claim
15 words
Checkpoint retry storage subsystem according to claim 2, characterized by a store-in level two cache.
Claim 5
Dependent Claim
15 words
Checkpoint retry storage subsystem according to claim 2, characterized by a store-through level one cache.
Claim 6
Dependent Claim
55 words
Checkpoint retry storage subsystem according to claim 1 characterized by instruction retry means responsive to an error signal for restoring said system to the condition which existed at said checkpoint signal, and wherein said instruction retry means further includes means for stopping said system during said restoration and for restarting said system after said restoration.
References Cited (Backward Citations)
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