US5075840A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Tightly coupled multiprocessor instruction synchronization
Assignee: International Business Machines Corp
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Filing: 1989-01-13
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Granted: 1991-12-24
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Expires: 2009-01-13
Abstract
Abstract A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.
Inventors
- 👤 Gregory F. Grohoski
- 👤 James A. Kahle
- 👤 Myhong Nguyenphu
- 👤 David S. Ray
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 02:26
CPC Classifications
G; G06; G06F; G06F7/00; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F9/30; G06F9/38; G06F9/3818; G06F9/3822; G06F9/3836; G06F9/3861; G06F9/3877; G06F9/3885
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
137 words
A data processing system comprising: an instruction storage means for storing a sequence of instructions requiring operation by at least two processor means; a plurality of processor means for executing instructions from said instruction storage means; instruction dispatch means, connected to said instruction storage means and said plurality of processors, for dispatching each instruction to at least one of said processor means; and at least one of said processor means including means, connected to said instruction dispatch means, for executing dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor means, and said executing means including means for delaying execution of an interruptible instruction for said processor means until said interruptible instruction is executed in its sequential order with the execution of other instructions in the sequence by other processor means.
Claim 2
Dependent Claim
137 words
A data processing system comprising: an instruction storage means for storing a sequence of instructions requiring operation by at least two processor means; a plurality of processor means for executing instructions from said instruction storage means; instruction dispatch means, connected to said instruction storage means and said plurality of processors, for dispatching each instruction to at least one of said processor means; and at least one of said processor means including means, connected to said instruction dispatch means, for executing dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor means, and said executing means including means for delaying execution of an interruptible instruction for said processor means until said interruptible instruction is executed in its sequential order with the execution of other instructions in the sequence by other processor means.
Claim 3
Dependent Claim
43 words
A data processing system according to claim 1 wherein said means for executing dispatched instructions before the execution of said preceding instruction further includes means for delaying execution of an instruction ahead of sequence when said instruction requires operations by another processor means.
Claim 4
Dependent Claim
43 words
A data processing system according to claim 2 wherein said instruction dispatch means includes means for detecting the occurrence of an interrupt and in response thereto, for dispatching instructions of the sequence in the order previously dispatched before the occurrence of the interrupt.
Claim 5
Dependent Claim
43 words
A data processing system according to claim 3 wherein said means for executing dispatched instructions before the execution of said preceding instruction further includes means for delaying execution of an instruction ahead of sequence when said instruction requires operation by another processor means.
Claim 6
Dependent Claim
40 words
A data processing systems according to claim 4 wherein said instruction storage means includes the sequence of instruction for the at least two processor means and the instruction dispatch means dispatches each instruction to the at least two processor means.
Claim 7
Dependent Claim
24 words
A data processing system according to claim 5 wherein said instruction sequence includes at least one instruction that requires the operations of two processors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-23 | 1995-06-24 | 1995-12-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-23 | 1999-06-24 | 1999-12-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-23 | 2003-06-24 | 2003-12-24 | $7700.00 | Window Closed / Lapsed |