Method of performing a sequence of related activities via multiple asynchronously intercoupled digital processors

Claim 3

A method according to claim 1 and further including the step of signaling said second processor in response to said INTERPROCESSOR NEXT instruction to re-execute said second activity if it is called again by yet another activity even while said third activity is being executed by said third processor.

Claim 4

A method according to claim 1 and further including the steps of: providing each activity with a queue containing pointers to the respective caller of that activity; and moving the caller pointer from the queue of the second activity into the queue of the third activity in response to said INTERPROCESSOR NEXT instruction.

Claim 5

A method according to claim 3 and further including the step of limiting access to said queues such that said pointers are loaded and unloaded during multiple cycles by only one of said processors at a time.

Claim 6

A method according to claim 1 and further including the step of executing another activity in said first processor while said first activity is suspended.

Claim 7

A data processing system including first, second and third digital processors which operate asynchronously to each other; said system being adapted to perform a task as a sequence of called activities of which some are not returned to when the sequence is complete, including: means for directing said first processor to execute a portion of a first activity in said sequence, said portion including and ending with an INTERPROCESSOR CALL instruction; means for signaling a second processor in response to said INTERPROCESSOR CALL instruction that a second activity has been called by said first activity and also suspending execution of said first activity; means for directing said second processor to completely execute said second activity and further execute an INTERPROCESSOR NEXT instruction which references a third activity in a third processor; means for signaling said third processor in response to said INTERPROCESSOR NEXT instruction that said third activity has been called not by said second activity but by whatever activity happened to call said second activity; and means for directing said third processor to completely execute said third activity, and upon completion thereof, to signal said third activity's apparent caller as indicated by said INTERPROCESSOR NEXT instruction to resume execution.

Claim 8

A data processing system including first, second and third digital processors which operate asynchronously to each other; said system being adapted to perform a task as a sequence of called activities of which some are not returned to when the sequence is complete, including: means for directing said first processor to execute a portion of a first activity in said sequence, said portion including and ending with an INTERPROCESSOR CALL instruction; means for signaling a second processor in response to said INTERPROCESSOR CALL instruction that a second activity has been called by said first activity and also suspending execution of said first activity; means for directing said second processor to completely execute said second activity and further execute an INTERPROCESSOR NEXT instruction which references a third activity in a third processor; means for signaling said third processor in response to said INTERPROCESSOR NEXT instruction that said third activity has been called not by said second activity but by whatever activity happened to call said second activity; and means for directing said third processor to completely execute said third activity, and upon completion thereof, to signal said third activity's apparent caller as indicated by said INTERPROCESSOR NEXT instruction to resume execution.

Claim 9

A system according to claim 6 and further including means for signaling said second processor to re-execute said second activity if it is called again by yet another activity even while said third activity is being executed by said third processor in response to said INTERPROCESSOR NEXT instruction.

Claim 10

A system according to claim 6 and further including: a queue means for each activity containing pointers to the respective caller of that activity; and means for moving the caller pointer from the queue of said second activity into the queue of said third activity in response to said INTERPROCESSOR NEXT instruction.

Claim 11

A system according to claim 8 and further including a means for limiting access to said queues such that said pointers are loaded and unloaded during multiple cycles by only one of said processors at a time.

Claim 12

A system according to claim 6 and further including means for executing another activity in the first processor while said first activity is suspended.