Store buffer apparatus in a multiprocessor system

Claim 1

A cache system for transferring data to and from a processor, said system comprising: a level two (L2) storage unit; a level one (L1) cache coupled to said processor and to said L2 storage unit; first means for writing data from said L2 storage unit to said L1 cache, and writing said data from said L1 cache to said processor; a level one (L1) storage unit coupled to said processor and said L2 storage unit; second means, responsive to a write request by said processor, for writing data from said processor to said L1 storage unit without first requiring contents of said L2 storage unit from an address associated with said write request be stored in said L1 cache or said L1 storage unit if said address is not currently represented in said L1 cache or said L1 storage unit, and subsequently writing said data from said L1 storage unit to said L2 storage unit, said second mean also writing said data to said L1 cache if said address is currently represented in said L1 cache; and status means, coupled t said L1 storage unit and responsive to a read request by said processor, for determining if said read request requires data that is stored in said L1 storage unit but has not yet been written from said L1 storage unit to said L2 storage unit, and if so, delaying said read request until the second writing means writes said data from said L1 storage unit to said L2 storage unit, and then causing said processor to a access said at a from said L1 cache if written in said L1 cache by said second means, without writing said data from said L2 storage unit to said L1 cache, if not, without said delay, causing said first means to write said data form said L1 cache to said processor if said data resides in said L1 cache or causing said first means to write said data from said L2 storage unit to said L1 cache and then from said L1 cache to said processor if said data did not reside in said L1 cache when said processor made said read request.