Data processing system having a data coherence solution

Claim 3

A system, according to claim 1, wherein said usage mode information identifies a public use, in which: (i) said addressable main memory means is the current owner of an address; (ii) said plurality of processor means may store in said addressable secondary memory means, respectively, valid copies of the data of the current owned address; and (iii) said addressable main memory means and said plurality of processor means cannot modify the data of the current owned address.

Claim 4

A system, according to claim 2, wherein said usage mode information identifies a private use, in which: (i) the current owner of an address can modify the data; and (ii) said addressable main memory means and said plurality of said processor means, other than the current owner, can have no valid copies of the data of the current owned address.

Claim 7

A system, according to claim 4, wherein said bus means supports a plurality of bus transactions including read request public, read request private, read response, write modified and write unmodified, and wherein each one of said plurality of processor means can generate command information for initiating said plurality of bus transactions on said bus, in which: (i) said read request public is initiated to acquire and read a copy of a block of data of an address; (ii) said read request private is initiated to acquire ownership of an address of a block of data and to modify the corresponding data of the address; (iii) said read response is initiated to respond to a read request public or a read request private of another of said plurality of processor means; (iv) said write modified is initiated to transfer ownership of an address owned by said one processor means, and the corresponding data, to said addressable main memory means, said corresponding data having been modified by said one processor means; and (v) said write unmodified is initiated to transfer ownership of an address owned by said one processor means to said addressable main memory means, the corresponding data having not been modified by said one processor means.

Claim 8

A system, according to claim 5, wherein, for said write unmodified bus transaction, the corresponding data of the address being transferred is not transferred to said addressable main memory means.

Claim 9

A system, according to claim 5, further comprising input processor means for inputting new data of a block having an address to said addressable main memory means, wherein said bus means supports another bus transaction being write new data, and wherein said input processor means generates command information to initiate said write new data to transfer ownership of the address of the new data from the current owner to said addressable main memory means.

Claim 10

A system, according to claim 5, wherein, upon initiation of said read request public or said read request private by said one processor means, the current owner of the address generates an acknowledgement signal to commit a read response.

Claim 11

A system, according to claim 8, wherein, upon generation of the acknowledgement signal for said read request private, ownership of the address is transferred from the current owner to said one processor means, followed by said current owner initiating a read response to transfer the block of data of the address to said one processor means.

Claim 12

A system, according to claim 9, wherein said one processor means, after acquiring ownership of the address and prior to the transfer of the block of data of the address to said one processor means, generates a busy signal upon a read request public or read request private initiated by another of said plurality of processor means and corresponding to the owned address.

Claim 13

A system, according to claim 10, further comprising input processor means for inputting new data of a block having an address to said addressable main memory means, wherein said bus means supports another bus transaction being write new data, and wherein said input processor means generates command information to initiate said write new data to transfer ownership of the address of the new data from the current owner to said addressable main memory means.

Claim 14

A system, according to claim 11, wherein said one processor means, after initiating a read request private and acquiring ownership of the address, and prior to the transfer of the block of data of the address to said one processor means, immediately loses ownership of the address in response to an acknowledgement signal by said addressable main memory means to said write new data and thereafter invalidates the data being transferred upon receipt by said one processor means of the data.

Claim 15

A system, according to claim 11, wherein said one processor means, after initiating a read request public and prior to the transfer of the block of data of the address to said one processor means, and in response to an acknowledgement signal by said addressable main memory means to said write new data or said read request private, invalidates the data being transferred immediately upon receipt of the data.

Claim 16

A system, according to claim 11, wherein said one processor means has a copy of data of an address being public, and said one processor means invalidates said copy of said data in response to said read request private or said write new data.

Claim 17

A tightly-coupled computer system for processing data partitioned into blocks of data, each block of data being identified by a unique address, comprising: (a) addressable main memory means for storing the blocks of data; (b) a plurality of processor means for accessing the blocks of data, each of said processor means having addressable cache memory means for storing a number of the blocks of data, addresses of the number of blocks of data and a plurality of flags per block of data stored in said addressable cache memory means, a first of said plurality of flags being a usage mode flag identifying if the corresponding address is public or private, a second of said plurality of flags being a modify flag identifying if the data of the corresponding block have been modified or are unmodified since being stored in said addressable cache memory means, and a third of said plurality of flags being a validity flag identifying if the data of the corresponding block are valid or invalid; (c) bus means for intercoupling said plurality of processor means with said addressable main memory means and for intercoupling each one of said plurality of processor means with any other of said plurality of processor means; (d) wherein only one of said addressable main memory means and said plurality of processor means is a current owner of an address of a block of data, wherein said current owner has the correct data for the owned address, and wherein ownership of an address is dynamically changeable among said addressable main memory means and said plurality of processor means; (e) wherein, if said usage mode flag is public, then (i) said addressable main memory means is the current owner of an address; (ii) said plurality of processor means may store in said addressable cache memory means, respectively, valid copies of the data of the current owned address, and (iii) said addressable main memory means and said plurality of processor means cannot modify the corresponding block of data; and (f) wherein, if said usage mode flag is private, then (i) the current owner of an address can modify the data; and (ii) said addressable main memory means and said plurality of processor means, other than the current owner, can have no valid copies of the data of the current owned address.

Claim 18

A tightly-coupled computer system for processing data partitioned into blocks of data, each block of data being identified by a unique address, comprising: (a) addressable main memory means for storing the blocks of data; (b) a plurality of processor means for accessing the blocks of data, each of said processor means having addressable cache memory means for storing a number of the blocks of data, addresses of the number of blocks of data and a plurality of flags per block of data stored in said addressable cache memory means, a first of said plurality of flags being a usage mode flag identifying if the corresponding address is public or private, a second of said plurality of flags being a modify flag identifying if the data of the corresponding block have been modified or are unmodified since being stored in said addressable cache memory means, and a third of said plurality of flags being a validity flag identifying if the data of the corresponding block are valid or invalid; (c) bus means for intercoupling said plurality of processor means with said addressable main memory means and for intercoupling each one of said plurality of processor means with any other of said plurality of processor means; (d) wherein only one of said addressable main memory means and said plurality of processor means is a current owner of an address of a block of data, wherein said current owner has the correct data for the owned address, and wherein ownership of an address is dynamically changeable among said addressable main memory means and said plurality of processor means; (e) wherein, if said usage mode flag is public, then (i) said addressable main memory means is the current owner of an address; (ii) said plurality of processor means may store in said addressable cache memory means, respectively, valid copies of the data of the current owned address, and (iii) said addressable main memory means and said plurality of processor means cannot modify the corresponding block of data; and (f) wherein, if said usage mode flag is private, then (i) the current owner of an address can modify the data; and (ii) said addressable main memory means and said plurality of processor means, other than the current owner, can have no valid copies of the data of the current owned address.

Claim 19

A tightly-coupled computer system according to claim 15 wherein one of said plurality of processor means can communicate directly with another of said plurality of processor means to transfer a given block of data between each without transferring the given block of data to the addressable main memory means.

Claim 20

A tightly-coupled computer system, according to claim 15, wherein each one of said plurality of processor means comprises: (a) processor subsystem means for accessing said number of blocks of data in said addressable cache memory means, said addressable cache memory means producing a cache status signal identifying a cache hit or a cache miss; (b) bus interface means for monitoring a plurality of bus transactions occurring on said bus means and for producing a bus monitor status signal identifying the bus transactions; and (c) means, responsive to the cache miss status signal or the bus monitor status signal, for initiating any one of the plurality of bus transactions, including (i) a read request public to acquire and read a copy of a block of data of an address; (ii) a read request private to acquire ownership of an address of a block of data and to modify the corresponding data of the address; (iii) a read response to respond to a read request public or a read request private of another of said plurality of processor means; (iv) a write modified to transfer ownership of an address owned by said one processor means, and the corresponding data, to said addressable main memory means, said corresponding data having been modified by said one processor means; and (v) a write unmodified to transfer ownership of an address owned by said one processor means to said addressable main memory means without transferring the corresponding data to said addressable main memory means, the corresponding data having not been modified by said one processor means.

Claim 21

A tightly-coupled computer system, according to claim 17, wherein, upon initiation of said read request public or said read request private by said one processor means, the current owner of the address generates an acknowledgement signal to commit a read response to said one processor means.

Claim 22

A tightly-coupled computer system, according to claim 18, wherein, upon the acknowledgment signal for said read request private, ownership of the address is transferred from the current owner to said one processor means.

Claim 23

A tightly-coupled computer system, according to claim 18, wherein, upon the acknowledgement signal for said read request public initiated by said one processor means, and prior to the transfer of the corresponding data to said one processor means, and upon receipt by said one processor means of a read request private initiated by another of said processor means prior to said transfer of the corresponding data, said one processor means writes said validity flag to invalidate the corresponding data.

Claim 24

A tightly-coupled computer system, according to claim 18, wherein said addressable cache memory means of said one processor means has a copy of data of an address being public, and wherein, upon receipt and acknowledgement by said one processor means of a read request private initiated by another of said processor means, said one processor means writes said validity flag to invalidate the copy of the data.

Claim 25

A tightly-coupled computer system, according to claim 18, further comprising input processor means for inputting new data of a block having an address to said addressable main memory means, wherein said bus means supports another bus transaction being a write new data, wherein said input processor means initiates said write new data upon inputting the new data, wherein said one processor means has an address corresponding to the new data, and wherein, in response to receipt by said one processor means of an acknowledgement signal of said write new data, said one processor means writes said validity flag to invalidate the data of the public address.

Claim 26

A tightly-coupled computer system, according to claim 22, wherein upon the acknowledgement signal for said read request private initiated by said one processor means, ownership of the address is immediately transferred by the current owner to said one processor means, followed by said current owner initiating a read response to transfer the corresponding data of the address to said one processor means.

Claim 27

A tightly-coupled computer system, according to claim 22, wherein, prior to the transfer of the corresponding data to said one processor means, and upon receipt by said one processor means of an acknowledgement of said write new data, said one processor means writes said validity flag to invalidate the corresponding data.

Claim 28

A tightly-coupled computer system, according to claim 22, wherein upon the acknowledgement signal for said read request public initiated by said one processor means, and prior to the transfer of the corresponding data to said one processor means, and upon receipt by said one processor means of an acknowledgement of said write new data prior to the transfer of the corresponding data, said one processor means writes said validity flag to invalidate the corresponding data.

Claim 29

A tightly-coupled computer system according to claim 18 wherein the current owner can generate a busy signal to require reinitiation of the read request public or read request private.

Claim 30

A single general purpose processor for connection to a computer system having an addressable main memory means for storing blocks of data, each block of data being identified by a unique address, at least one other general purpose processor, and an expansion bus supporting a plurality of bus transactions and intercoupling each said general purpose processor with each other said general purpose processor and for intercoupling each said general purpose processor with said addressable main memory means, said single general purpose processor comprising: (a) addressable cache memory means for storing a number of said blocks of data and addresses of said number of blocks of data; (b) subsystem processor means for accessing said addressable cache memory means to read or write data, said addressable cache memory means generating a cache status signal identifying a cache hit or a cache miss; (c) bus interface means for coupling blocks of data between said addressable cache memory means and the expansion bus, said bus interface means including means for monitoring the plurality of bus transactions on the expansion bus and generating an expansion bus monitor status signal identifying the plurality of bus transactions; and (d) microengine means for initiating the plurality of bus transactions, respectively, in response to said cache miss status signal and in response to said expansion bus monitor status signal.

Claim 31

A single general purpose processor for connection to a computer system having an addressable main memory means for storing blocks of data, each block of data being identified by a unique address, at least one other general purpose processor, and an expansion bus supporting a plurality of bus transactions and intercoupling each said general purpose processor with each other said general purpose processor and for intercoupling each said general purpose processor with said addressable main memory means, said single general purpose processor comprising: (a) addressable cache memory means for storing a number of said blocks of data and addresses of said number of blocks of data; (b) subsystem processor means for accessing said addressable cache memory means to read or write data, said addressable cache memory means generating a cache status signal identifying a cache hit or a cache miss; (c) bus interface means for coupling blocks of data between said addressable cache memory means and the expansion bus, said bus interface means including means for monitoring the plurality of bus transactions on the expansion bus and generating an expansion bus monitor status signal identifying the plurality of bus transactions; and (d) microengine means for initiating the plurality of bus transactions, respectively, in response to said cache miss status signal and in response to said expansion bus monitor status signal.

Claim 32

A single general purpose processor, according to claim 27, wherein only one of the addressable main memory means and each said general purpose processor is an owner of an address of a block of data and wherein ownership of an address of a block of data is dynamically changeable among the addressable main memory means and each said general purpose processor, and wherein said microengine means initiates command information identifying the plurality of bus transactions, said command information comprising: (a) a read request public to acquire a copy of, and read, a block data of an address for storage in said addressable cache memory means; (b) a read request private to acquire ownership of an address of a block of data and to modify the corresponding data to be stored in said addressable cache memory means; (c) a read response to respond to a read request public or read request private of another said general purpose processor; (d) a write modified to transfer ownership of an address owned by said single general purpose processor, and the corresponding data, to the adressable main memory means, said corresponding data having been modified by said sysbsystem processor means since being stored in said addressable cache memory means; and (e) a write unmodified to transfer ownership of an address owned by said single general purpose processor to the addressable main memory means, the corresponding data having not been modified by said subsystem processor means.

Claim 33

A single general purpose processor, according to claim 28, wherein said microengine means generates an address to acquire a corresponding block of data in response to the cache miss status signal.

Claim 34

A single general purpose processor, according to claim 27, wherein said subsystem processor means generates an address to access said addressable cache memory means.

Claim 35

A single general purpose processor, according to claim 30, wherein said addressable cache memory means comprises: (a) a cache memory for storing the blocks of data; (b) data cache tag means, responsive to the address generated by said subsystem processor means, for storing a number of addresses corresponding to the blocks of data of said cache memory; and (c) a control circuit, coupled to said data cache tag means, for controlling access to said cache memory, said cache control circuit generating said cache status signal.

Claim 36

A single general purpose processor, according to claim 27, wherein an address further has associated with it a validity flag identifying if corresponding data are valid or invalid, a modify flag identifying if corresponding data have been modified or have not been modified since being stored in said addressable cache memory means, and a usage mode flag identifying if the address is public or private, and wherein said microengine means includes means for writing said validity flag, said modified flag and said usage mode flag.

Claim 37

An expansion bus for supporting a plurality of bus transactions among an addressable main memory means for storing blocks of data and a plurality of processor means for processing the data, each of said plurality of processor means having a secondary memory means for storing a number of blocks of the data, said addressable main memory means and one or more of said plurality of processor means being connected to said expansion bus, each block of data having associated with it an address and a public or private usage mode identifying the use that can be made of the data, said expansion bus carrying command data identifying said plurality of bus transactions, said command data comprising: (a) a read request public being a bus transaction for acquiring and reading the data; (b) a read request private being a bus transaction for acquiring and modifying the data; (c) a read response being a bus transaction for responding to a read request public or a read request private; (d) a write modified being a bus transaction for transferring modified data of an address to the addressable main memory means; and (e) a write unmodified being a bus transaction for transferring ownership of an address to the addressable main memory means.

Claim 38

An expansion bus for supporting a plurality of bus transactions among an addressable main memory means for storing blocks of data and a plurality of processor means for processing the data, each of said plurality of processor means having a secondary memory means for storing a number of blocks of the data, said addressable main memory means and one or more of said plurality of processor means being connected to said expansion bus, each block of data having associated with it an address and a public or private usage mode identifying the use that can be made of the data, said expansion bus carrying command data identifying said plurality of bus transactions, said command data comprising: (a) a read request public being a bus transaction for acquiring and reading the data; (b) a read request private being a bus transaction for acquiring and modifying the data; (c) a read response being a bus transaction for responding to a read request public or a read request private; (d) a write modified being a bus transaction for transferring modified data of an address to the addressable main memory means; and (e) a write unmodified being a bus transaction for transferring ownership of an address to the addressable main memory means.

Claim 39

An expansion bus, according to claim 33, further comprising a write new data being a bus transaction for writing new data to, and transferring ownership of an address to, the addressable main memory means.

Claim 40

An expansion bus, according to claim 33, wherein each of said plurality of bus exchanges is unidirectional among the plurality of processor means and the addressable main memory means.

Claim 41

An expansion bus, according to claim 33, wherein each of said plurality of bus transactions is performed over time slots.

Claim 42

An expansion bus, according to claim 36, wherein said read request public comprises a read address being bussed over one time slot.

Claim 43

An expansion bus, according to claim 36, wherein said read request private comprises a read address being bussed over one time slot.

Claim 44

An expansion bus, according to claim 36, wherein said read response comprises data being bussed over a plurality of consecutive time slots.

Claim 45

An expansion bus, according to claim 26, wherein said write modified comprises a write address being bussed over one time slot followed beginning at the next time slot by data being bussed over a plurality of consecutive time slots.

Claim 46

An expansion bus, according to claim 36, wherein said write unmodified comprises a write address being bussed over one time slot.

Claim 47

An expansion bus, according to claim 36, wherein said write new data comprises a write address being bussed over one time slot followed beginning at the next time slot by data being bussed over a plurality of consecutive time slots.

Claim 48

An expansion bus for supporting communication among an addressable main memory means for storing data and a plurality of processor means for processing blocks of data, each of said plurality of processor means having a secondary memory means for storing the data, said addressable main memory means and one or more of said plurality of processor means being connected to the expansion bus, each block of data having associated with it a usage mode identifying the use that can be made of the block of data, said expansion bus carrying three functional groups of signals being transmitted during relative time slots, said three functional groups including: (a) an arbitration group of signals for enabling any one of the plurality of processor means to request and acquire said expansion bus; (b) an information group of signals for enabling any of the plurality of processor means to perform any of a plurality of bus transactions, including (i) a read request public being a bus transaction for acquiring and reading the data; (ii) a read request private being a bus transaction for acquiring and modifying the data; (iii) a read response being a bus transaction for responding to a read request public or a read request private; (iv) a write modified being a bus transaction for transferring modified data of an address to the addressable main memory means; and (v) a write unmodified being a bus transaction for transferring ownership of an address to the addressable main memory means; and (c) an acknowledge group of signals for acknowledgement receipt of said information group.

Claim 49

An expansion bus for supporting communication among an addressable main memory means for storing data and a plurality of processor means for processing blocks of data, each of said plurality of processor means having a secondary memory means for storing the data, said addressable main memory means and one or more of said plurality of processor means being connected to the expansion bus, each block of data having associated with it a usage mode identifying the use that can be made of the block of data, said expansion bus carrying three functional groups of signals being transmitted during relative time slots, said three functional groups including: (a) an arbitration group of signals for enabling any one of the plurality of processor means to request and acquire said expansion bus; (b) an information group of signals for enabling any of the plurality of processor means to perform any of a plurality of bus transactions, including (i) a read request public being a bus transaction for acquiring and reading the data; (ii) a read request private being a bus transaction for acquiring and modifying the data; (iii) a read response being a bus transaction for responding to a read request public or a read request private; (iv) a write modified being a bus transaction for transferring modified data of an address to the addressable main memory means; and (v) a write unmodified being a bus transaction for transferring ownership of an address to the addressable main memory means; and (c) an acknowledge group of signals for acknowledgement receipt of said information group.

Claim 50

An expansion bus, according to claim 42, wherein said relative time slots are such that said information group is provided over a time slot n, said arbitration group is provided over a time slot n-1, and said acknowledge group is provided over a time slot n+2.

Claim 51

An expansion bus, according to claim 43, wherein said information group comprises command data identifying any one of said plurality of bus transactions.

Claim 52

An expansion bus, according to claim 43, wherein said acknowledge group comprises a first acknowledge signal being producable by the addressable main memory means and a second acknowledge signal being producable by any of the plurality of processor means.

Claim 53

An expansion bus, according to claim 43, for further supporting communication between the addressable main memory means and an input processor means for inputting new data to the addressable main memory means, and wherein said plurality of bus transactions of said information group further comprises a write new data being a bus transaction for writing new data to, and transferring ownership of an address to, the addressable main memory means.

Claim 54

A processor for connection to a bus carrying plurality of bus transactions, comprising: (a) means for producing a read request public bus transaction to acquire and read data; (b) means for producing a read request private bus transaction to acquire ownership of and modify data; (c) means for producing a read response bus transaction to respond to a read request public or private bus transaction of another said processor; (d) means for producing a write modified bus transaction to relinquish ownership of and transfer modified data onto the bus; and (e) means for producing a write unmodified bus transaction to relinquish ownership of unmodified data without transferring the unmodified data onto the bus.

Claim 55

A processor for connection to a bus carrying plurality of bus transactions, comprising: (a) means for producing a read request public bus transaction to acquire and read data; (b) means for producing a read request private bus transaction to acquire ownership of and modify data; (c) means for producing a read response bus transaction to respond to a read request public or private bus transaction of another said processor; (d) means for producing a write modified bus transaction to relinquish ownership of and transfer modified data onto the bus; and (e) means for producing a write unmodified bus transaction to relinquish ownership of unmodified data without transferring the unmodified data onto the bus.

Claim 56

A processor, according to claim 48, wherein said processor is a general purpose processor.