US4394731A — Cache storage line shareability control for a mul…

Claim 1

Independent Claim 435 words

A multiprocessor (MP) system having at least two processors, in which each processor has a processor store-in-cache, and a processor cache directory (PD) with a plurality of line entries for corresponding line positions in the associated cache, the MP system further comprising, each processor requesting its PD for main storage access with either an exclusive (EX) or readonly (RO) shareability signal, an exclusive (EX) bit position, a line change (CH) bit position, a valid (V) bit position, and an address field being provided in each PD line entry, the opposite states of the EX bit position indicating exclusive or readonly shareability for the corresponding line position, cache miss detecting means connected to each PD for generating a storage line fetch and cross-interrogation (XI) command from each cache miss, the XI command indicating if the initiating processor request has an exclusive or readonly signal and is a fetch or store request and indicating a main storage address for the request, cross-interrogation (XI) means connected to receive each XI command, control means connected to receive the output of the XI means and searching valid line entries represented in each other PD in the MP system for detecting any existing conflicting line having the main storage address indicated in the XI command, testing means associated with each PD and connected to receive each XI command for testing the state of the EX bit position in any entry found to represent a conflicting line, and if the EX bit is set to the exclusive state also testing the CH bit for the conflicting line, means connected to each cache for casting out any conflicting line from the associated cache if the testing means senses the CH bit is on, and setting off the V bit position in the associated PD entry for the conflicting line, means in the associated PD for the conflicting line for setting the EX bit position to the readonly state if the CH bit position is off and not casting out the line which then remains valid in its processor cache, inter-cache means connected between the processors in the MP for setting an EX bit position to readonly state in a line entry for the storage line fetch in the PD which generated the XI command when the EX bit position in each entry for the conflicting line is set to readonly state, whereby readonly cache sharing is permitted for the line obtained by the storage line fetch found to have a conflicting line in another cache in a non-changed state, even though the initiating processor request is for exclusive control of the requested data.

Claim 2

Dependent Claim 435 words

A multiprocessor (MP) system having at least two processors, in which each processor has a processor store-in-cache, and a processor cache directory (PD) with a plurality of line entries for corresponding line positions in the associated cache, the MP system further comprising, each processor requesting its PD for main storage access with either an exclusive (EX) or readonly (RO) shareability signal, an exclusive (EX) bit position, a line change (CH) bit position, a valid (V) bit position, and an address field being provided in each PD line entry, the opposite states of the EX bit position indicating exclusive or readonly shareability for the corresponding line position, cache miss detecting means connected to each PD for generating a storage line fetch and cross-interrogation (XI) command from each cache miss, the XI command indicating if the initiating processor request has an exclusive or readonly signal and is a fetch or store request and indicating a main storage address for the request, cross-interrogation (XI) means connected to receive each XI command, control means connected to receive the output of the XI means and searching valid line entries represented in each other PD in the MP system for detecting any existing conflicting line having the main storage address indicated in the XI command, testing means associated with each PD and connected to receive each XI command for testing the state of the EX bit position in any entry found to represent a conflicting line, and if the EX bit is set to the exclusive state also testing the CH bit for the conflicting line, means connected to each cache for casting out any conflicting line from the associated cache if the testing means senses the CH bit is on, and setting off the V bit position in the associated PD entry for the conflicting line, means in the associated PD for the conflicting line for setting the EX bit position to the readonly state if the CH bit position is off and not casting out the line which then remains valid in its processor cache, inter-cache means connected between the processors in the MP for setting an EX bit position to readonly state in a line entry for the storage line fetch in the PD which generated the XI command when the EX bit position in each entry for the conflicting line is set to readonly state, whereby readonly cache sharing is permitted for the line obtained by the storage line fetch found to have a conflicting line in another cache in a non-changed state, even though the initiating processor request is for exclusive control of the requested data.

Claim 3

Dependent Claim 81 words

A MP system as defined in claim 1, further comprising a copy directory (CD) provided for each PD, each CD having respective line entries containing information copied from a related PD, each entry in the CD having a copy of the EX, V and address field found in a corresponding line entry in the related PD, the control means searching all CDs for a line entry in each CD having the main storage address indicated in the XI command being searched.

Claim 4

Dependent Claim 55 words

A MP system as defined in claim 2, the control means further comprising plural CD control means for respectively searching each CD for the address in the XI command, and each CD control means generating a conflict signal upon finding a conflicting entry having an address field equal to the address in the XI command.

Claim 5

Dependent Claim 59 words

A MP system as defined in claim 3, each CD control means further comprising, CD command generating means for providing a CD test command to the related PD upon sensing a XI command having a processor fetch request with an exclusive signal and finding the EX bit set to exclusive state in the CD entry for the conflicting line.

Claim 6

Dependent Claim 42 words

A MP system as defined in claim 4, the testing means further comprising, test command registering means for receiving the CD test command, and circuit means for testing the state of the CH bit position for the conflicting line in the PD.

Claim 7

Dependent Claim 59 words

A MP system as defined in claim 5, further comprising plural buffer control elements (BCEs) respectively associated with the PDs, each BCE receiving each processor request for its associated PD and searching and controlling the associated PD and its cache, and the testing means being contained in each BCE for receiving the CD test command from the related CD.

Claim 8

Dependent Claim 61 words

A MP system as defined in claim 6, each BCE further comprising BCE command generating means for providing a BCE command to the related CD control means for changing a related CD entry to readonly (CERO) state, and the related CD control means receiving the CERO BCE command and setting the EX bit in the related CD entry to readonly state.

Claim 9

Dependent Claim 109 words

A MP system as defined in claim 7, the inter-cache means further comprising an alter-to-readonly (ATRO) bistable circuit means associated with each CD and being activated by the related CD control means after the reception of the CERO BCE command from the related BCE, inter-processor bus means for sending the ATRO signal from the CD control means for the CD having a conflict to the CD control means for the processor initiating the XI command, EX control means in the initiating processor for setting the EX bit to readonly state in the line fetch entry in the initiating processor CD and PD in response to a received ATRO signal.

Claim 10

Dependent Claim 85 words

A MP system as defined in claim 8, the EX control means further comprising ROD means with each CD control means for generating a readonly designation (ROD) signal at the end of each XI operation in the CD control means for the initiating processor in response to an ATRO signal being received from any processor CD control means, the EX control means setting the EX bit to readonly state in the line fetch entry in the issuing processor PD when activated by a ROD signal.

Claim 11

Dependent Claim 290 words

A MP system having at least two processors, in which each processor has a processor store-in-cache, and a processor cache director (PD) with a plurality of line entries for corresponding line positions in the processor cache, the MP system further comprising, each processor having request means signalling if the processor exclusively requests its PD for a fetch or store access of its cache, an exclusive (EX) bit position, a line change (CH) bit position, a valid (V) bit position, and an address field being provided in each line entry in each PD, means for setting the EX bit position in the assigned line position to exclusive state in response to an exclusive request from the associated processor, PD line request means connected to each PD for being initiated by a processor request which does not find the requested data in the associated processor cache, means for assigning a line position in the associated PD for the requested line to be fetched, means connecting a corresponding copy directory (CD) to each PD for a respective processor, each CD line entry having an EX bit position, a V bit position and an address field set to the same values as a corresponding line entry in the related PD, XI register means connected to each CD for receiving each PD line request identifying the requesting processor, whether the processor request is a fetch or store, the request address, and if requested exclusively or readonly, XI priority means connected to each CD for each PD line request to initiate all CD control means to search all CDs for any conflicting line entry having the request address and to test the state of the EX bit in any conflicting line entry found in any CD.

Claim 12

Dependent Claim 290 words

A MP system having at least two processors, in which each processor has a processor store-in-cache, and a processor cache director (PD) with a plurality of line entries for corresponding line positions in the processor cache, the MP system further comprising, each processor having request means signalling if the processor exclusively requests its PD for a fetch or store access of its cache, an exclusive (EX) bit position, a line change (CH) bit position, a valid (V) bit position, and an address field being provided in each line entry in each PD, means for setting the EX bit position in the assigned line position to exclusive state in response to an exclusive request from the associated processor, PD line request means connected to each PD for being initiated by a processor request which does not find the requested data in the associated processor cache, means for assigning a line position in the associated PD for the requested line to be fetched, means connecting a corresponding copy directory (CD) to each PD for a respective processor, each CD line entry having an EX bit position, a V bit position and an address field set to the same values as a corresponding line entry in the related PD, XI register means connected to each CD for receiving each PD line request identifying the requesting processor, whether the processor request is a fetch or store, the request address, and if requested exclusively or readonly, XI priority means connected to each CD for each PD line request to initiate all CD control means to search all CDs for any conflicting line entry having the request address and to test the state of the EX bit in any conflicting line entry found in any CD.

Claim 13

Dependent Claim 183 words

A MP system as defined in claim 10, further comprising means for sending a test command to the PD if the CD control means finds the EX bit is in exclusive state for the conflicting line, means for detecting the state of the CH bit position for the conflicting line entry in the related PD, means for casting out the conflicting line from the associated processor cache if the CH bit is on and thereafter setting off the V bit in each entry for the castout line in the related PD and CD, and PD command means for setting the EX bit position to the readonly state if the CH bit position is off to indicate the conflicting line was not changed and that the conflicting line remains available in the corresponding processor cache, whereby an exclusive processor fetch request causing a cache miss results in simultaneous cache sharing being permitted for the line if it is found in another cache in a non-changed state, although cache sharing is not permitted if the line is found in another cache in a changed state.

Claim 14

Dependent Claim 110 words

A MP system as defined in claims 10 or 11, further comprising inter-processor communication means for signalling from the CD control means finding a conflicting line entry to a CD control means for the processor initiating the PD line request, means for activating an alter to readonly (ATRO) signal on said inter-processor communication means when the EX bit in the conflicting line entry is set to readonly state, whether the EX bit for the conflicting entry was found during the CD search to be in the readonly state, or whether the EX bit was found to be in exclusive state and changed to readonly state by a resulting PD command.

Claim 15

Dependent Claim 78 words

A MP system as defined in claim 12, the EX control means further comprising ROD means with the CD control means for the issuing processor generating a readonly designation (ROD) signal at the end of each XI operation in response to an ATRO signal being received from any processor CD control means, EX control means in the issuing processor PD setting the EX bit to readonly state in the line fetch entry in response to the ROD signal.

Claim 16

Dependent Claim 28 words

A MP system as defined in claim 12, further comprising at least one system controller having a plurality of CD control means and a corresponding plurality of CDs.

Claim 17

Dependent Claim 53 words

A MP system as defined in claim 12, further comprising, a plurality of system controllers, means connecting each system controller to at least one processor in the MP, cross-interrogation bus means being contained in the inter-processor communication means for communicating a XI command from any XI register means to each CD control means.

Claim 18

Dependent Claim 34 words

A MP system as defined in claim 14, in which the MP system has one system controller connected to at least two processors in the MP, the system controller containing two CD control means.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1986-07-18	1987-01-17	1987-07-19	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1990-07-18	1991-01-17	1991-07-19	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1994-07-18	1995-01-17	1995-07-19	$7700.00	Window Closed / Lapsed

Cache storage line shareability control for a multiprocessor system

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