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US3771137A Expired / Lapsed US ⏱️ 0.0 years remaining

Memory control in a multipurpose system utilizing a broadcast

Assignee: International Business Machines Corp
•
Filing: 1971-09-10
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Granted: 1973-11-06
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Expires: 1991-09-10
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Abstract

Abstract In a multiprocessing computer where a plurality of processors, each with its own buffer memory, share a main memory, a broadcast system provides each processor the capability to query each other processor to determine whether a modified (e.g. updated) version of the desired data is located in another processor''s buffer memory. The memory control unit simultaneously initiates a main memory read cycle and a broadcast signal in response to a request for data. If a modified version of the data is found to be in a buffer memory, it is transferred to the main memory by the control unit. The main memory read cycle is then changed to a write cycle so that the modified version replaces the original data. The modified data is then switched onto the memory data bus and transmitted to the requesting processor. Using this system, which only allows one buffer to contain a modified version of any data item, the requesting processor obtains the most current data in one main memory cycle in such a manner that it appears that the data is originating from main memory.

Inventors

  • 👤 R Barner
  • 👤 J Deveer
  • 👤 J Oblonsky

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-22 16:44
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0833

Claims Analysis

Total Claims: 27
Claim 1
Independent Claim 286 words
A memory control system in a data processing system with a main memory and a plurality of data processors, each processor having the capability to modify data, and including its own buffer memory unit in which to retain data comprising: system control means; circuit means associated with said control means for selectively connecting said main memory to each of said plurality of data processors; first means within said control means for initiating a query on behalf of a requesting data processor regarding the availability of requested data in said main memory; second means within said control means for initiating a second query regarding the availability of a modified version of the requested data within any one of the aforesaid buffer memory units; validation means within said buffer memory unit for indicating, in response to the second query, the one of the aforesaid buffer memory units containing the modified version of data; third means within said control means for initiating a data retrieval from said main memory to the requesting data processor concurrent with the second query to each of the aforesaid buffer memory units; means within said control means for detecting the state of said validation means; means controlled by sAid detecting means for interrupting the initiated main memory data retrieval fetch function said initiating a main memory data store function when the state of said validation means indicates that one of the aforesaid buffer memory units contains the modified version of data; and means operable concurrently with said interruption means for transmitting the modified version of data from the buffer memory unit so containing the modified version of data to the buffer memory unit of the requesting processor and simultaneously therewith to said main memory.
Claim 2
Dependent Claim 286 words
A memory control system in a data processing system with a main memory and a plurality of data processors, each processor having the capability to modify data, and including its own buffer memory unit in which to retain data comprising: system control means; circuit means associated with said control means for selectively connecting said main memory to each of said plurality of data processors; first means within said control means for initiating a query on behalf of a requesting data processor regarding the availability of requested data in said main memory; second means within said control means for initiating a second query regarding the availability of a modified version of the requested data within any one of the aforesaid buffer memory units; validation means within said buffer memory unit for indicating, in response to the second query, the one of the aforesaid buffer memory units containing the modified version of data; third means within said control means for initiating a data retrieval from said main memory to the requesting data processor concurrent with the second query to each of the aforesaid buffer memory units; means within said control means for detecting the state of said validation means; means controlled by sAid detecting means for interrupting the initiated main memory data retrieval fetch function said initiating a main memory data store function when the state of said validation means indicates that one of the aforesaid buffer memory units contains the modified version of data; and means operable concurrently with said interruption means for transmitting the modified version of data from the buffer memory unit so containing the modified version of data to the buffer memory unit of the requesting processor and simultaneously therewith to said main memory.
Claim 3
Dependent Claim 22 words
The apparatus of claim 1 wherein each of said plurality of data processors includes at least an input/output channel and a uniprocessor.
Claim 4
Dependent Claim 11 words
Initiating a read cycle of main memory for said requested data,
Claim 5
Dependent Claim 11 words
Initiating a read cycle of main memory for said requested data,
Claim 6
Dependent Claim 19 words
Querying processors buffer memorys for a modified version of requested data concurrent with said initiation of a read cycle,
Claim 7
Dependent Claim 19 words
Querying processors buffer memorys for a modified version of requested data concurrent with said initiation of a read cycle,
Claim 8
Dependent Claim 19 words
The apparatus of claim 1 wherein said data processors are a plurality of processors within a multi-processing computer system.
Claim 9
Dependent Claim 28 words
The apparatus of claim 3 wherein said second means initiates said query to all buffer memory units other than to the buffer memory unit of said requesting processor.
Claim 10
Dependent Claim 12 words
Detecting a modified version of data in one of said buffer memorys.
Claim 11
Dependent Claim 12 words
Detecting a modified version of data in one of said buffer memorys.
Claim 12
Dependent Claim 19 words
Converting said read cycle to a write cycle when modified data is discovered as a result of said query,
Claim 13
Dependent Claim 19 words
Converting said read cycle to a write cycle when modified data is discovered as a result of said query,
Claim 14
Dependent Claim 38 words
The apparatus of claim 4 wherein said second means initiates said query to buffer memory units consequent upon the unavailability of said requested data in a valid form in the buffer memory unit of said requesting data processor.
Claim 15
Dependent Claim 37 words
The apparatus of claim 5 wherein said validation means comprises a validity bit stored in a directory associated with each portion of said data in each of said buffer memories to indicate whether the data is valid.
Claim 16
Dependent Claim 7 words
Writing said modified data into main memory.
Claim 17
Dependent Claim 7 words
Writing said modified data into main memory.
Claim 18
Dependent Claim 12 words
Transmitting said modified data to said requesting processor concurrently with said writing.
Claim 19
Dependent Claim 12 words
Transmitting said modified data to said requesting processor concurrently with said writing.
Claim 20
Dependent Claim 43 words
The apparatus of claim 6 wherein said validation means further comprises a modified bit stored in a directory associated with each portion of said data in each of said buffer memories to indicate whether the data has been modified by said data processor.
Claim 21
Dependent Claim 34 words
The apparatus of claim 7 wherein said control means comprises a plurality of control units each connected to a data processor, the main memory and the other control units associated with other data processors.
Claim 22
Dependent Claim 38 words
The apparatus of claim 8 wherein said control unit associated with said requesting data processor operates simultaneously with the operation of the other control units when broadcasting its requesting data and initiates said data retrieval from main memory.
Claim 23
Dependent Claim 55 words
The apparatus of claim 9 wherein said control unit associated with said buffer memory, wherein a modified version of data was indicated, further contains means to control said conversion of said data retrieval to a data storage of said modified data into main memory and means to transmit said modified data to the requesting processor.
Claim 24
Dependent Claim 31 words
The apparatus of claim 10 further comprising means to query only the requesting data processor when a store operation is desired to main memory from said requesting data processor''s buffer memory.
Claim 25
Dependent Claim 25 words
The apparatus of claim 11 further comprising means within said control units to determine whether the requested data is located in its associated buffer memory.
Claim 26
Independent Claim 25 words
A method of obtaining data in a data processing system which contains multiple users each with its own buffer memory unit comprising the steps of:
Claim 27
Independent Claim 25 words
A method of obtaining data in a data processing system which contains multiple users each with its own buffer memory unit comprising the steps of:

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-11-05 1977-05-07 1977-11-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-11-05 1981-05-07 1981-11-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-11-05 1985-05-07 1985-11-06 $7700.00 Window Closed / Lapsed

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